1 //===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Lanai implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H 15 #define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H 16 17 #include "LanaiRegisterInfo.h" 18 #include "MCTargetDesc/LanaiMCTargetDesc.h" 19 #include "llvm/CodeGen/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #include "LanaiGenInstrInfo.inc" 23 24 namespace llvm { 25 26 class LanaiInstrInfo : public LanaiGenInstrInfo { 27 const LanaiRegisterInfo RegisterInfo; 28 29 public: 30 LanaiInstrInfo(); 31 32 // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 33 // such, whenever a client has an instance of instruction info, it should 34 // always be able to get register info as well (through this method). 35 virtual const LanaiRegisterInfo &getRegisterInfo() const { 36 return RegisterInfo; 37 } 38 39 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb, 40 AliasAnalysis *AA) const override; 41 42 unsigned isLoadFromStackSlot(const MachineInstr &MI, 43 int &FrameIndex) const override; 44 45 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, 46 int &FrameIndex) const override; 47 48 unsigned isStoreToStackSlot(const MachineInstr &MI, 49 int &FrameIndex) const override; 50 51 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, 52 const DebugLoc &DL, unsigned DestinationRegister, 53 unsigned SourceRegister, bool KillSource) const override; 54 55 void 56 storeRegToStackSlot(MachineBasicBlock &MBB, 57 MachineBasicBlock::iterator Position, 58 unsigned SourceRegister, bool IsKill, int FrameIndex, 59 const TargetRegisterClass *RegisterClass, 60 const TargetRegisterInfo *RegisterInfo) const override; 61 62 void 63 loadRegFromStackSlot(MachineBasicBlock &MBB, 64 MachineBasicBlock::iterator Position, 65 unsigned DestinationRegister, int FrameIndex, 66 const TargetRegisterClass *RegisterClass, 67 const TargetRegisterInfo *RegisterInfo) const override; 68 69 bool expandPostRAPseudo(MachineInstr &MI) const override; 70 71 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, 72 int64_t &Offset, 73 const TargetRegisterInfo *TRI) const override; 74 75 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg, 76 int64_t &Offset, unsigned &Width, 77 const TargetRegisterInfo *TRI) const; 78 79 std::pair<unsigned, unsigned> 80 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 81 82 ArrayRef<std::pair<unsigned, const char *>> 83 getSerializableDirectMachineOperandTargetFlags() const override; 84 85 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, 86 MachineBasicBlock *&FalseBlock, 87 SmallVectorImpl<MachineOperand> &Condition, 88 bool AllowModify) const override; 89 90 unsigned removeBranch(MachineBasicBlock &MBB, 91 int *BytesRemoved = nullptr) const override; 92 93 // For a comparison instruction, return the source registers in SrcReg and 94 // SrcReg2 if having two register operands, and the value it compares against 95 // in CmpValue. Return true if the comparison instruction can be analyzed. 96 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 97 unsigned &SrcReg2, int &CmpMask, 98 int &CmpValue) const override; 99 100 // See if the comparison instruction can be converted into something more 101 // efficient. E.g., on Lanai register-register instructions can set the flag 102 // register, obviating the need for a separate compare. 103 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, 104 unsigned SrcReg2, int CmpMask, int CmpValue, 105 const MachineRegisterInfo *MRI) const override; 106 107 // Analyze the given select instruction, returning true if it cannot be 108 // understood. It is assumed that MI->isSelect() is true. 109 // 110 // When successful, return the controlling condition and the operands that 111 // determine the true and false result values. 112 // 113 // Result = SELECT Cond, TrueOp, FalseOp 114 // 115 // Lanai can optimize certain select instructions, for example by predicating 116 // the instruction defining one of the operands and sets Optimizable to true. 117 bool analyzeSelect(const MachineInstr &MI, 118 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp, 119 unsigned &FalseOp, bool &Optimizable) const override; 120 121 // Given a select instruction that was understood by analyzeSelect and 122 // returned Optimizable = true, attempt to optimize MI by merging it with one 123 // of its operands. Returns NULL on failure. 124 // 125 // When successful, returns the new select instruction. The client is 126 // responsible for deleting MI. 127 // 128 // If both sides of the select can be optimized, the TrueOp is modifed. 129 // PreferFalse is not used. 130 MachineInstr *optimizeSelect(MachineInstr &MI, 131 SmallPtrSetImpl<MachineInstr *> &SeenMIs, 132 bool PreferFalse) const override; 133 134 bool reverseBranchCondition( 135 SmallVectorImpl<MachineOperand> &Condition) const override; 136 137 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, 138 MachineBasicBlock *FalseBlock, 139 ArrayRef<MachineOperand> Condition, 140 const DebugLoc &DL, 141 int *BytesAdded = nullptr) const override; 142 }; 143 144 static inline bool isSPLSOpcode(unsigned Opcode) { 145 switch (Opcode) { 146 case Lanai::LDBs_RI: 147 case Lanai::LDBz_RI: 148 case Lanai::LDHs_RI: 149 case Lanai::LDHz_RI: 150 case Lanai::STB_RI: 151 case Lanai::STH_RI: 152 return true; 153 default: 154 return false; 155 } 156 } 157 158 static inline bool isRMOpcode(unsigned Opcode) { 159 switch (Opcode) { 160 case Lanai::LDW_RI: 161 case Lanai::SW_RI: 162 return true; 163 default: 164 return false; 165 } 166 } 167 168 static inline bool isRRMOpcode(unsigned Opcode) { 169 switch (Opcode) { 170 case Lanai::LDBs_RR: 171 case Lanai::LDBz_RR: 172 case Lanai::LDHs_RR: 173 case Lanai::LDHz_RR: 174 case Lanai::LDWz_RR: 175 case Lanai::LDW_RR: 176 case Lanai::STB_RR: 177 case Lanai::STH_RR: 178 case Lanai::SW_RR: 179 return true; 180 default: 181 return false; 182 } 183 } 184 185 } // namespace llvm 186 187 #endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H 188
