| /external/llvm/lib/CodeGen/ |
| RegUsageInfoCollector.cpp | 15 /// MRI::isPhysRegUsed() then creates a RegMask based on this details.
16 /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
62 void markRegClobbered(const TargetRegisterInfo *TRI, uint32_t *RegMask,
80 uint32_t *RegMask, unsigned PReg) {
83 RegMask[*AI / 32] &= ~(1u << *AI % 32);
101 std::vector<uint32_t> RegMask;
107 RegMask.resize(RegMaskSize, 0xFFFFFFFF);
119 markRegClobbered(TRI, &RegMask[0], PReg);
126 RegMask[i] = RegMask[i] | CallPreservedMask[i]
[all...] |
| RegUsageInfoPropagate.cpp | 14 /// each callsite queries RegisterUsageInfo for RegMask (calculated based on
15 /// actual register allocation) of the callee function, if the RegMask detail
16 /// is available then this pass will update the RegMask of the call instruction.
17 /// This updated RegMask will be used by the register allocator while allocating
64 static void setRegMask(MachineInstr &MI, const uint32_t *RegMask) {
67 MO.setRegMask(RegMask);
109 const auto *RegMask = PRUI->getRegUsageInfo(F);
110 if (!RegMask)
112 setRegMask(MI, &(*RegMask)[0]);
|
| RegisterUsageInfo.cpp | 50 const Function *FP, std::vector<uint32_t> RegMask) {
52 RegMasks[FP] = std::move(RegMask);
70 for (const auto &RegMask : RegMasks)
71 FPRMPairVector.push_back(&RegMask);
|
| MachineCopyPropagation.cpp | 95 /// Remove any entry in \p Map that is marked clobbered in \p RegMask.
96 /// The map will typically have a lot fewer entries than the regmask clobbers,
100 const MachineOperand &RegMask) {
105 if (RegMask.clobbersPhysReg(Reg))
256 const MachineOperand *RegMask = nullptr;
259 RegMask = &MO;
296 if (RegMask) {
305 if (!RegMask->clobbersPhysReg(Reg)) {
310 DEBUG(dbgs() << "MCP: Removing copy due to regmask clobbering: ";
321 removeClobberedRegsFromMap(AvailCopyMap, *RegMask);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| RegUsageInfoPropagate.cpp | 14 /// each callsite queries RegisterUsageInfo for RegMask (calculated based on
15 /// actual register allocation) of the callee function, if the RegMask detail
16 /// is available then this pass will update the RegMask of the call instruction.
17 /// This updated RegMask will be used by the register allocator while allocating
65 static void setRegMask(MachineInstr &MI, ArrayRef<uint32_t> RegMask) {
66 assert(RegMask.size() ==
73 MO.setRegMask(RegMask.data());
126 const ArrayRef<uint32_t> RegMask = PRUI->getRegUsageInfo(F);
127 if (RegMask.empty())
129 setRegMask(MI, RegMask);
[all...] |
| RegisterUsageInfo.cpp | 61 const Function &FP, ArrayRef<uint32_t> RegMask) {
62 RegMasks[&FP] = RegMask;
79 for (const auto &RegMask : RegMasks)
80 FPRMPairVector.push_back(&RegMask);
|
| RegUsageInfoCollector.cpp | 15 /// MRI::isPhysRegUsed() then creates a RegMask based on this details.
16 /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
90 std::vector<uint32_t> RegMask;
96 RegMask.resize(RegMaskSize, ~((uint32_t)0));
109 auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
110 RegMask[Reg / 32] &= ~(1u << Reg % 32);
113 // function set it and all the aliasing registers as defined in the regmask.
140 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
145 PRUI.storeUpdateRegUsageInfo(F, RegMask);
|
| LiveRegUnits.cpp | 27 void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) {
30 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg))
36 void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) {
39 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg))
46 // Remove defined registers and regmask kills from the set.
71 // Add defs, uses and regmask clobbers to the set.
|
| MachineCopyPropagation.cpp | 150 /// Remove any entry in \p Map that is marked clobbered in \p RegMask.
151 /// The map will typically have a lot fewer entries than the regmask clobbers,
155 const MachineOperand &RegMask) {
160 if (RegMask.clobbersPhysReg(Reg))
504 const MachineOperand *RegMask = nullptr;
507 RegMask = &MO;
527 if (RegMask) {
536 if (!RegMask->clobbersPhysReg(Reg)) {
541 LLVM_DEBUG(dbgs() << "MCP: Removing copy due to regmask clobbering: ";
552 removeClobberedRegsFromMap(AvailCopyMap, *RegMask);
[all...] |
| MachineOperand.cpp | 33 PrintRegMaskNumRegs("print-regmask-num-regs",
35 "printing regmask operands in IR dumps. "
295 const uint32_t *RegMask = getRegMask();
297 if (RegMask == OtherRegMask)
301 // Calculate the size of the RegMask
306 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
308 // We don't know the size of the RegMask, so we can't deep compare the two
847 OS << "<regmask";
872 const uint32_t *RegMask = getRegLiveOut()
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| RegisterUsageInfo.h | 50 /// To store RegMask for given Function *.
52 ArrayRef<uint32_t> RegMask);
54 /// To query stored RegMask for given Function *, it will returns ane empty
61 /// A Dense map from Function * to RegMask.
62 /// In RegMask 0 means register used (clobbered) by function.
|
| LiveRegUnits.h | 109 /// Removes register units not preserved by the regmask \p RegMask.
110 /// The regmask has the same format as the one in the RegMask machine operand.
111 void removeRegsNotPreserved(const uint32_t *RegMask);
113 /// Adds register units not preserved by the regmask \p RegMask.
114 /// The regmask has the same format as the one in the RegMask machine operand.
115 void addRegsInMask(const uint32_t *RegMask);
[all...] |
| MachineOperand.h | 169 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
597 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
601 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
604 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
607 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
612 /// getRegMask - Returns a bit mask of registers preserved by this RegMask
616 return Contents.RegMask;
619 /// Returns number of elements needed for a regmask array.
627 return Contents.RegMask;
684 Contents.RegMask = RegMaskPtr
[all...] |
| MachineRegisterInfo.h | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| RegisterUsageInfo.h | 55 /// To store RegMask for given Function *.
57 std::vector<uint32_t> RegMask);
59 /// To query stored RegMask for given Function *, it will return nullptr if
66 /// A Dense map from Function * to RegMask.
67 /// In RegMask 0 means register used (clobbered) by function.
|
| MachineOperand.h | 159 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
471 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
475 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
478 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
481 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
486 /// getRegMask - Returns a bit mask of registers preserved by this RegMask
490 return Contents.RegMask;
496 return Contents.RegMask;
543 Contents.RegMask = RegMaskPtr;
694 /// A RegMask operand represents a set of non-clobbered physical registers o
[all...] |
| MachineRegisterInfo.h | 717 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
719 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
720 UsedPhysRegMask.setBitsNotInMask(RegMask);
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceRegAlloc.h | 36 void scan(const SmallBitVector &RegMask, bool Randomized);
66 SmallBitVector RegMask;
|
| IceRegAlloc.cpp | 87 const SmallBitVector &RegMask,
90 for (RegNumT i : RegNumBVIter(RegMask)) {
417 // Remove from RegMask any physical registers referenced during Cur's live
425 Iter.RegMask[RegAlias] = false;
434 const RegNumT RegNum = *RegNumBVIter(Iter.RegMask).begin();
532 // That register must be one in the RegMask set, e.g. don't try to prefer
535 const int SrcReg = (Iter.RegMask & Aliases).find_first();
690 int32_t MinWeightIndex = findMinWeightIndex(Iter.RegMask, Iter.Weights);
[all...] |
| IceTargetLowering.cpp | 522 SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude);
527 LinearScan.scan(RegMask, getFlags().getRandomizeRegisterAllocation());
538 postRegallocSplitting(RegMask);
572 void TargetLowering::postRegallocSplitting(const SmallBitVector &RegMask) {
656 RegAlloc.scan(RegMask, getFlags().getRandomizeRegisterAllocation());
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64CollectLOH.cpp | 450 static void handleRegMaskClobber(const uint32_t *RegMask, MCPhysReg Reg,
452 if (!MachineOperand::clobbersPhysReg(RegMask, Reg))
463 const uint32_t *RegMask = MO.getRegMask();
465 handleRegMaskClobber(RegMask, Reg, LOHInfos);
467 handleRegMaskClobber(RegMask, Reg, LOHInfos);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 415 // Read the branch mask, target (if applicable), regmask (if applicable).
422 const uint32_t *RegMask;
424 RegMask = MBBI->getOperand(2).getRegMask();
430 // Remove target (branch) or regmask (sibcall).
453 MIB.addRegMask(RegMask);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 536 // Read the branch mask, target (if applicable), regmask (if applicable).
543 const uint32_t *RegMask;
545 RegMask = MBBI->getOperand(2).getRegMask();
551 // Remove target (branch) or regmask (sibcall).
579 MIB.addRegMask(RegMask);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 456 const uint32_t *RegMask = getCallPreservedMask(MF, CC);
457 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
|
