| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPURegisterInfo.cpp | 40 static const unsigned SubRegs[] = {
47 assert(Channel < array_lengthof(SubRegs));
48 return SubRegs[Channel];
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| AMDGPURegisterInfo.cpp | 31 static const unsigned SubRegs[] = {
38 assert(Channel < array_lengthof(SubRegs));
39 return SubRegs[Channel];
|
| SIInstrInfo.cpp | [all...] |
| /external/capstone/ |
| MCRegisterInfo.h | 45 /// register. The SubRegs field is a zero terminated array of registers that
53 uint32_t SubRegs; // Sub-register set, described above
57 // sub-register in SubRegs.
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsFrameLowering.cpp | 220 const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
223 MachineLocation SrcML0(*SubRegs);
224 MachineLocation SrcML1(*(SubRegs + 1));
|
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| MCRegisterInfo.h | 111 /// alias EAX. The SubRegs field is a zero terminated array of registers that
120 const unsigned *SubRegs; // Sub-register set, described above
235 return get(RegNo).SubRegs;
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| CodeGenRegisters.h | 53 return SubRegs;
83 SubRegMap SubRegs;
|
| CodeGenRegisters.cpp | 52 return SubRegs;
55 std::vector<Record*> SubList = TheDef->getValueAsListOfDefs("SubRegs");
59 " SubRegIndices doesn't match SubRegs");
61 // First insert the direct subregs and make sure they are fully indexed.
64 if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second)
69 // Keep track of inherited subregs and how they can be reached.
72 // Clone inherited subregs and place duplicate entries on Orphans.
73 // Here the order is important - earlier subregs take precedence.
85 if (!SubRegs.insert(*SI).second)
124 SubRegs[BaseIdxInit->getDef()] = R2
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 99 /// register. The SubRegs field is a zero terminated array of registers that
107 uint32_t SubRegs; // Sub-register set, described above
111 // sub-register in SubRegs.
472 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 99 /// register. The SubRegs field is a zero terminated array of registers that
107 uint32_t SubRegs; // Sub-register set, described above
111 // sub-register in SubRegs.
494 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
|
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 158 return SubRegs;
251 SubRegMap SubRegs;
|
| CodeGenRegisters.cpp | 119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
123 "SubRegs and SubRegIndices must have the same size");
131 // covered-by-subregs super-registers where it appears as the first explicit
204 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
218 return SubRegs;
223 // First insert the explicit subregs and make sure they are fully indexed.
227 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
235 // Keep track of inherited subregs and how they can be reached.
238 // Clone inherited subregs and place duplicate entries in Orphans
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 184 return SubRegs;
277 SubRegMap SubRegs;
|
| CodeGenRegisters.cpp | 170 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
174 "SubRegs and SubRegIndices must have the same size");
182 // covered-by-subregs super-registers where it appears as the first explicit
257 for (const auto &SubReg : SubRegs) {
270 return SubRegs;
275 // First insert the explicit subregs and make sure they are fully indexed.
281 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
289 // Keep track of inherited subregs and how they can be reached.
292 // Clone inherited subregs and place duplicate entries in Orphans.
293 // Here the order is important - earlier subregs take precedence
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 148 const unsigned SubRegs[]);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 759 unsigned SubRegs = 0;
766 SubRegs = 2;
770 SubRegs = 4;
775 SubRegs = 2;
779 SubRegs = 3;
783 SubRegs = 4;
787 SubRegs = 2;
791 SubRegs = 2;
796 SubRegs = 3;
801 SubRegs = 4
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 149 const unsigned SubRegs[]);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 846 unsigned SubRegs = 0;
853 SubRegs = 2;
857 SubRegs = 4;
862 SubRegs = 2;
866 SubRegs = 3;
870 SubRegs = 4;
874 SubRegs = 2;
878 SubRegs = 2;
883 SubRegs = 3;
888 SubRegs = 4
[all...] |
