1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Parent TargetRegisterInfo class common to all hw codegen targets. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "AMDGPURegisterInfo.h" 16 #include "AMDGPUTargetMachine.h" 17 18 using namespace llvm; 19 20 AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {} 21 22 //===----------------------------------------------------------------------===// 23 // Function handling callbacks - Functions are a seldom used feature of GPUS, so 24 // they are not supported at this time. 25 //===----------------------------------------------------------------------===// 26 27 // Dummy to not crash RegisterClassInfo. 28 static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister; 29 30 const MCPhysReg *AMDGPURegisterInfo::getCalleeSavedRegs( 31 const MachineFunction *) const { 32 return &CalleeSavedReg; 33 } 34 35 unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const { 36 return AMDGPU::NoRegister; 37 } 38 39 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const { 40 static const unsigned SubRegs[] = { 41 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4, 42 AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9, 43 AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, 44 AMDGPU::sub15 45 }; 46 47 assert(Channel < array_lengthof(SubRegs)); 48 return SubRegs[Channel]; 49 } 50 51 #define GET_REGINFO_TARGET_DESC 52 #include "AMDGPUGenRegisterInfo.inc" 53
