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      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /*
      3  * (C) Copyright 2011-2013
      4  * Texas Instruments, <www.ti.com>
      5  *
      6  * For more details, please see the TRM at http://www.ti.com/product/tps65910
      7  */
      8 #ifndef __POWER_TPS65910_H__
      9 #define __POWER_TPS65910_H__
     10 
     11 #define MPU     0
     12 #define CORE    1
     13 
     14 #define TPS65910_SR_I2C_ADDR				0x12
     15 #define TPS65910_CTRL_I2C_ADDR				0x2D
     16 
     17 /* PMIC Register offsets */
     18 enum {
     19 	TPS65910_VDD1_REG				= 0x21,
     20 	TPS65910_VDD1_OP_REG				= 0x22,
     21 	TPS65910_VDD2_REG				= 0x24,
     22 	TPS65910_VDD2_OP_REG				= 0x25,
     23 	TPS65910_DEVCTRL_REG				= 0x3F,
     24 };
     25 
     26 /* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
     27 #define TPS65910_VGAIN_SEL_MASK				(0x3 << 6)
     28 #define TPS65910_ILMAX_MASK				(0x1 << 5)
     29 #define TPS65910_TSTEP_MASK				(0x7 << 2)
     30 #define TPS65910_ST_MASK				(0x3)
     31 
     32 #define TPS65910_REG_VGAIN_SEL_X1			(0x0 << 6)
     33 #define TPS65910_REG_VGAIN_SEL_X1_0			(0x1 << 6)
     34 #define TPS65910_REG_VGAIN_SEL_X3			(0x2 << 6)
     35 #define TPS65910_REG_VGAIN_SEL_X4			(0x3 << 6)
     36 
     37 #define TPS65910_REG_ILMAX_1_0_A			(0x0 << 5)
     38 #define TPS65910_REG_ILMAX_1_5_A			(0x1 << 5)
     39 
     40 #define TPS65910_REG_TSTEP_				(0x0 << 2)
     41 #define TPS65910_REG_TSTEP_12_5				(0x1 << 2)
     42 #define TPS65910_REG_TSTEP_9_4				(0x2 << 2)
     43 #define TPS65910_REG_TSTEP_7_5				(0x3 << 2)
     44 #define TPS65910_REG_TSTEP_6_25				(0x4 << 2)
     45 #define TPS65910_REG_TSTEP_4_7				(0x5 << 2)
     46 #define TPS65910_REG_TSTEP_3_12				(0x6 << 2)
     47 #define TPS65910_REG_TSTEP_2_5				(0x7 << 2)
     48 
     49 #define TPS65910_REG_ST_OFF				(0x0)
     50 #define TPS65910_REG_ST_ON_HI_POW			(0x1)
     51 #define TPS65910_REG_ST_OFF_1				(0x2)
     52 #define TPS65910_REG_ST_ON_LOW_POW			(0x3)
     53 
     54 
     55 /* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
     56 #define TPS65910_OP_REG_SEL				(0x7F)
     57 
     58 #define TPS65910_OP_REG_CMD_MASK			(0x1 << 7)
     59 #define TPS65910_OP_REG_CMD_OP				(0x0 << 7)
     60 #define TPS65910_OP_REG_CMD_SR				(0x1 << 7)
     61 
     62 #define TPS65910_OP_REG_SEL_MASK			(0x7F)
     63 #define TPS65910_OP_REG_SEL_0_9_5			(0x1F)	/* 0.9500 V */
     64 #define TPS65910_OP_REG_SEL_1_1_0			(0x2B)	/* 1.1000 V */
     65 #define TPS65910_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
     66 #define TPS65910_OP_REG_SEL_1_2_0			(0x33)	/* 1.2000 V */
     67 #define TPS65910_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
     68 #define TPS65910_OP_REG_SEL_1_3_2_5			(0x3D)	/* 1.3250 V */
     69 
     70 /* Device control register . (DEVCTRL_REG) */
     71 #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK		(0x1 << 4)
     72 #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C	(0x0 << 4)
     73 #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C	(0x1 << 4)
     74 
     75 int tps65910_set_i2c_control(void);
     76 int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
     77 #endif	/* __POWER_TPS65910_H__ */
     78