1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2012 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T4240 QDS board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_FSL_SATA_V2 13 #define CONFIG_PCIE4 14 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 19 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 20 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 22 #else 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 25 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 26 #define CONFIG_SPL_PAD_TO 0x40000 27 #define CONFIG_SPL_MAX_SIZE 0x28000 28 #define RESET_VECTOR_OFFSET 0x27FFC 29 #define BOOT_PAGE_OFFSET 0x27000 30 31 #ifdef CONFIG_NAND 32 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 33 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 34 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 35 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 36 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 37 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg 38 #define CONFIG_SPL_NAND_BOOT 39 #endif 40 41 #ifdef CONFIG_SDCARD 42 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 43 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 44 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 45 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 46 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 47 #ifndef CONFIG_SPL_BUILD 48 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 49 #endif 50 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg 52 #define CONFIG_SPL_MMC_BOOT 53 #endif 54 55 #ifdef CONFIG_SPL_BUILD 56 #define CONFIG_SPL_SKIP_RELOCATE 57 #define CONFIG_SPL_COMMON_INIT_DDR 58 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 59 #endif 60 61 #endif 62 #endif /* CONFIG_RAMBOOT_PBL */ 63 64 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 65 /* Set 1M boot space */ 66 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 67 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 68 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 69 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 70 #endif 71 72 #define CONFIG_SRIO_PCIE_BOOT_MASTER 73 #define CONFIG_DDR_ECC 74 75 #include "t4qds.h" 76 77 #ifndef CONFIG_MTD_NOR_FLASH 78 #else 79 #define CONFIG_FLASH_CFI_DRIVER 80 #define CONFIG_SYS_FLASH_CFI 81 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 82 #endif 83 84 #if defined(CONFIG_SPIFLASH) 85 #define CONFIG_SYS_EXTRA_ENV_RELOC 86 #define CONFIG_ENV_SPI_BUS 0 87 #define CONFIG_ENV_SPI_CS 0 88 #define CONFIG_ENV_SPI_MAX_HZ 10000000 89 #define CONFIG_ENV_SPI_MODE 0 90 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 91 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 92 #define CONFIG_ENV_SECT_SIZE 0x10000 93 #elif defined(CONFIG_SDCARD) 94 #define CONFIG_SYS_EXTRA_ENV_RELOC 95 #define CONFIG_SYS_MMC_ENV_DEV 0 96 #define CONFIG_ENV_SIZE 0x2000 97 #define CONFIG_ENV_OFFSET (512 * 0x800) 98 #elif defined(CONFIG_NAND) 99 #define CONFIG_SYS_EXTRA_ENV_RELOC 100 #define CONFIG_ENV_SIZE 0x2000 101 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 102 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 103 #define CONFIG_ENV_ADDR 0xffe20000 104 #define CONFIG_ENV_SIZE 0x2000 105 #elif defined(CONFIG_ENV_IS_NOWHERE) 106 #define CONFIG_ENV_SIZE 0x2000 107 #else 108 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 109 #define CONFIG_ENV_SIZE 0x2000 110 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 111 #endif 112 113 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 114 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 115 116 #ifndef __ASSEMBLY__ 117 unsigned long get_board_sys_clk(void); 118 unsigned long get_board_ddr_clk(void); 119 #endif 120 121 /* EEPROM */ 122 #define CONFIG_ID_EEPROM 123 #define CONFIG_SYS_I2C_EEPROM_NXID 124 #define CONFIG_SYS_EEPROM_BUS_NUM 0 125 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 127 128 /* 129 * DDR Setup 130 */ 131 #define CONFIG_SYS_SPD_BUS_NUM 0 132 #define SPD_EEPROM_ADDRESS1 0x51 133 #define SPD_EEPROM_ADDRESS2 0x52 134 #define SPD_EEPROM_ADDRESS3 0x53 135 #define SPD_EEPROM_ADDRESS4 0x54 136 #define SPD_EEPROM_ADDRESS5 0x55 137 #define SPD_EEPROM_ADDRESS6 0x56 138 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 139 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 140 141 /* 142 * IFC Definitions 143 */ 144 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 145 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 146 + 0x8000000) | \ 147 CSPR_PORT_SIZE_16 | \ 148 CSPR_MSEL_NOR | \ 149 CSPR_V) 150 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 151 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 152 CSPR_PORT_SIZE_16 | \ 153 CSPR_MSEL_NOR | \ 154 CSPR_V) 155 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 156 /* NOR Flash Timing Params */ 157 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 158 159 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 160 FTIM0_NOR_TEADC(0x5) | \ 161 FTIM0_NOR_TEAHC(0x5)) 162 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 163 FTIM1_NOR_TRAD_NOR(0x1A) |\ 164 FTIM1_NOR_TSEQRAD_NOR(0x13)) 165 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 166 FTIM2_NOR_TCH(0x4) | \ 167 FTIM2_NOR_TWPH(0x0E) | \ 168 FTIM2_NOR_TWP(0x1c)) 169 #define CONFIG_SYS_NOR_FTIM3 0x0 170 171 #define CONFIG_SYS_FLASH_QUIET_TEST 172 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 173 174 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 175 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 176 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 177 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 178 179 #define CONFIG_SYS_FLASH_EMPTY_INFO 180 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 181 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 182 183 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 184 #define QIXIS_BASE 0xffdf0000 185 #define QIXIS_LBMAP_SWITCH 6 186 #define QIXIS_LBMAP_MASK 0x0f 187 #define QIXIS_LBMAP_SHIFT 0 188 #define QIXIS_LBMAP_DFLTBANK 0x00 189 #define QIXIS_LBMAP_ALTBANK 0x04 190 #define QIXIS_RST_CTL_RESET 0x83 191 #define QIXIS_RST_FORCE_MEM 0x1 192 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 193 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 194 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 195 #define QIXIS_BRDCFG5 0x55 196 #define QIXIS_MUX_SDHC 2 197 #define QIXIS_MUX_SDHC_WIDTH8 1 198 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 199 200 #define CONFIG_SYS_CSPR3_EXT (0xf) 201 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 202 | CSPR_PORT_SIZE_8 \ 203 | CSPR_MSEL_GPCM \ 204 | CSPR_V) 205 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 206 #define CONFIG_SYS_CSOR3 0x0 207 /* QIXIS Timing parameters for IFC CS3 */ 208 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 209 FTIM0_GPCM_TEADC(0x0e) | \ 210 FTIM0_GPCM_TEAHC(0x0e)) 211 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 212 FTIM1_GPCM_TRAD(0x3f)) 213 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 214 FTIM2_GPCM_TCH(0x8) | \ 215 FTIM2_GPCM_TWP(0x1f)) 216 #define CONFIG_SYS_CS3_FTIM3 0x0 217 218 /* NAND Flash on IFC */ 219 #define CONFIG_NAND_FSL_IFC 220 #define CONFIG_SYS_NAND_BASE 0xff800000 221 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 222 223 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 224 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 225 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 226 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 227 | CSPR_V) 228 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 229 230 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 231 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 232 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 233 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 234 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 235 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 236 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 237 238 #define CONFIG_SYS_NAND_ONFI_DETECTION 239 240 /* ONFI NAND Flash mode0 Timing Params */ 241 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 242 FTIM0_NAND_TWP(0x18) | \ 243 FTIM0_NAND_TWCHT(0x07) | \ 244 FTIM0_NAND_TWH(0x0a)) 245 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 246 FTIM1_NAND_TWBE(0x39) | \ 247 FTIM1_NAND_TRR(0x0e) | \ 248 FTIM1_NAND_TRP(0x18)) 249 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 250 FTIM2_NAND_TREH(0x0a) | \ 251 FTIM2_NAND_TWHRE(0x1e)) 252 #define CONFIG_SYS_NAND_FTIM3 0x0 253 254 #define CONFIG_SYS_NAND_DDR_LAW 11 255 256 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 257 #define CONFIG_SYS_MAX_NAND_DEVICE 1 258 259 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 260 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 261 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 262 263 #if defined(CONFIG_NAND) 264 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 265 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 266 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 267 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 268 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 269 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 270 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 271 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 272 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 273 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 274 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 275 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 276 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 277 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 278 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 279 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 280 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 281 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 282 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 283 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 284 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 285 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 286 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 287 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 288 #else 289 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 290 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 291 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 292 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 293 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 294 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 295 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 296 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 297 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 298 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 299 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 300 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 301 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 302 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 303 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 304 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 305 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 306 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 307 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 308 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 309 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 310 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 311 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 312 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 313 #endif 314 315 #if defined(CONFIG_RAMBOOT_PBL) 316 #define CONFIG_SYS_RAMBOOT 317 #endif 318 319 /* I2C */ 320 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 321 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 322 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 323 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 324 325 #define I2C_MUX_CH_DEFAULT 0x8 326 #define I2C_MUX_CH_VOL_MONITOR 0xa 327 #define I2C_MUX_CH_VSC3316_FS 0xc 328 #define I2C_MUX_CH_VSC3316_BS 0xd 329 330 /* Voltage monitor on channel 2*/ 331 #define I2C_VOL_MONITOR_ADDR 0x40 332 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 333 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 334 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 335 336 /* VSC Crossbar switches */ 337 #define CONFIG_VSC_CROSSBAR 338 #define VSC3316_FSM_TX_ADDR 0x70 339 #define VSC3316_FSM_RX_ADDR 0x71 340 341 /* 342 * RapidIO 343 */ 344 345 /* 346 * for slave u-boot IMAGE instored in master memory space, 347 * PHYS must be aligned based on the SIZE 348 */ 349 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 353 /* 354 * for slave UCODE and ENV instored in master memory space, 355 * PHYS must be aligned based on the SIZE 356 */ 357 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 360 361 /* slave core release by master*/ 362 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 363 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 364 365 /* 366 * SRIO_PCIE_BOOT - SLAVE 367 */ 368 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 369 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 370 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 371 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 372 #endif 373 /* 374 * eSPI - Enhanced SPI 375 */ 376 #define CONFIG_SF_DEFAULT_SPEED 10000000 377 #define CONFIG_SF_DEFAULT_MODE 0 378 379 /* Qman/Bman */ 380 #ifndef CONFIG_NOBQFMAN 381 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 382 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 383 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 384 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 385 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 386 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 387 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 388 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 389 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 390 CONFIG_SYS_BMAN_CENA_SIZE) 391 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 392 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 393 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 394 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 395 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 396 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 397 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 398 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 399 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 400 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 401 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 402 CONFIG_SYS_QMAN_CENA_SIZE) 403 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 404 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 405 406 #define CONFIG_SYS_DPAA_FMAN 407 #define CONFIG_SYS_DPAA_PME 408 #define CONFIG_SYS_PMAN 409 #define CONFIG_SYS_DPAA_DCE 410 #define CONFIG_SYS_DPAA_RMAN 411 #define CONFIG_SYS_INTERLAKEN 412 413 /* Default address of microcode for the Linux Fman driver */ 414 #if defined(CONFIG_SPIFLASH) 415 /* 416 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 417 * env, so we got 0x110000. 418 */ 419 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 420 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 421 #elif defined(CONFIG_SDCARD) 422 /* 423 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 424 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 425 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 426 */ 427 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 428 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 429 #elif defined(CONFIG_NAND) 430 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 431 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 432 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 433 /* 434 * Slave has no ucode locally, it can fetch this from remote. When implementing 435 * in two corenet boards, slave's ucode could be stored in master's memory 436 * space, the address can be mapped from slave TLB->slave LAW-> 437 * slave SRIO or PCIE outbound window->master inbound window-> 438 * master LAW->the ucode address in master's memory space. 439 */ 440 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 441 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 442 #else 443 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 444 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 445 #endif 446 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 447 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 448 #endif /* CONFIG_NOBQFMAN */ 449 450 #ifdef CONFIG_SYS_DPAA_FMAN 451 #define CONFIG_FMAN_ENET 452 #define CONFIG_PHYLIB_10G 453 #define CONFIG_PHY_VITESSE 454 #define CONFIG_PHY_TERANETICS 455 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 456 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 457 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 458 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 459 #define FM1_10GEC1_PHY_ADDR 0x0 460 #define FM1_10GEC2_PHY_ADDR 0x1 461 #define FM2_10GEC1_PHY_ADDR 0x2 462 #define FM2_10GEC2_PHY_ADDR 0x3 463 #endif 464 465 /* SATA */ 466 #ifdef CONFIG_FSL_SATA_V2 467 #define CONFIG_SYS_SATA_MAX_DEVICE 2 468 #define CONFIG_SATA1 469 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 470 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 471 #define CONFIG_SATA2 472 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 473 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 474 475 #define CONFIG_LBA48 476 #endif 477 478 #ifdef CONFIG_FMAN_ENET 479 #define CONFIG_MII /* MII PHY management */ 480 #define CONFIG_ETHPRIME "FM1@DTSEC1" 481 #endif 482 483 /* 484 * USB 485 */ 486 #define CONFIG_USB_EHCI_FSL 487 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 488 #define CONFIG_HAS_FSL_DR_USB 489 490 #ifdef CONFIG_MMC 491 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 492 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 493 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 494 #define CONFIG_ESDHC_DETECT_QUIRK \ 495 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 496 IS_SVR_REV(get_svr(), 1, 0)) 497 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 498 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 499 #endif 500 501 502 #define __USB_PHY_TYPE utmi 503 504 /* 505 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 506 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 507 * interleaving. It can be cacheline, page, bank, superbank. 508 * See doc/README.fsl-ddr for details. 509 */ 510 #ifdef CONFIG_ARCH_T4240 511 #define CTRL_INTLV_PREFERED 3way_4KB 512 #else 513 #define CTRL_INTLV_PREFERED cacheline 514 #endif 515 516 #define CONFIG_EXTRA_ENV_SETTINGS \ 517 "hwconfig=fsl_ddr:" \ 518 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 519 "bank_intlv=auto;" \ 520 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 521 "netdev=eth0\0" \ 522 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 523 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 524 "tftpflash=tftpboot $loadaddr $uboot && " \ 525 "protect off $ubootaddr +$filesize && " \ 526 "erase $ubootaddr +$filesize && " \ 527 "cp.b $loadaddr $ubootaddr $filesize && " \ 528 "protect on $ubootaddr +$filesize && " \ 529 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 530 "consoledev=ttyS0\0" \ 531 "ramdiskaddr=2000000\0" \ 532 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 533 "fdtaddr=1e00000\0" \ 534 "fdtfile=t4240qds/t4240qds.dtb\0" \ 535 "bdev=sda3\0" 536 537 #define CONFIG_HVBOOT \ 538 "setenv bootargs config-addr=0x60000000; " \ 539 "bootm 0x01000000 - 0x00f00000" 540 541 #define CONFIG_ALU \ 542 "setenv bootargs root=/dev/$bdev rw " \ 543 "console=$consoledev,$baudrate $othbootargs;" \ 544 "cpu 1 release 0x01000000 - - -;" \ 545 "cpu 2 release 0x01000000 - - -;" \ 546 "cpu 3 release 0x01000000 - - -;" \ 547 "cpu 4 release 0x01000000 - - -;" \ 548 "cpu 5 release 0x01000000 - - -;" \ 549 "cpu 6 release 0x01000000 - - -;" \ 550 "cpu 7 release 0x01000000 - - -;" \ 551 "go 0x01000000" 552 553 #define CONFIG_LINUX \ 554 "setenv bootargs root=/dev/ram rw " \ 555 "console=$consoledev,$baudrate $othbootargs;" \ 556 "setenv ramdiskaddr 0x02000000;" \ 557 "setenv fdtaddr 0x00c00000;" \ 558 "setenv loadaddr 0x1000000;" \ 559 "bootm $loadaddr $ramdiskaddr $fdtaddr" 560 561 #define CONFIG_HDBOOT \ 562 "setenv bootargs root=/dev/$bdev rw " \ 563 "console=$consoledev,$baudrate $othbootargs;" \ 564 "tftp $loadaddr $bootfile;" \ 565 "tftp $fdtaddr $fdtfile;" \ 566 "bootm $loadaddr - $fdtaddr" 567 568 #define CONFIG_NFSBOOTCOMMAND \ 569 "setenv bootargs root=/dev/nfs rw " \ 570 "nfsroot=$serverip:$rootpath " \ 571 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 572 "console=$consoledev,$baudrate $othbootargs;" \ 573 "tftp $loadaddr $bootfile;" \ 574 "tftp $fdtaddr $fdtfile;" \ 575 "bootm $loadaddr - $fdtaddr" 576 577 #define CONFIG_RAMBOOTCOMMAND \ 578 "setenv bootargs root=/dev/ram rw " \ 579 "console=$consoledev,$baudrate $othbootargs;" \ 580 "tftp $ramdiskaddr $ramdiskfile;" \ 581 "tftp $loadaddr $bootfile;" \ 582 "tftp $fdtaddr $fdtfile;" \ 583 "bootm $loadaddr $ramdiskaddr $fdtaddr" 584 585 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 586 587 #include <asm/fsl_secure_boot.h> 588 589 #endif /* __CONFIG_H */ 590
