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  /external/u-boot/arch/arm/lib/
bootm-fdt.c 39 int bank; local
43 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
44 start[bank] = bd->bi_dram[bank].start;
45 size[bank] = bd->bi_dram[bank].size;
47 ret = armv7_apply_memory_carveout(&start[bank], &size[bank]);
    [all...]
  /external/u-boot/arch/arm/mach-imx/mx5/
soc.c 78 struct fuse_bank *bank = &iim->bank[1]; local
80 (struct fuse_bank1_regs *)bank->fuse_regs;
  /external/u-boot/arch/arm/mach-sunxi/
pinmux.c 22 u32 bank = GPIO_BANK(pin); local
23 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
42 u32 bank = GPIO_BANK(pin); local
43 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
50 u32 bank = GPIO_BANK(pin); local
53 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
62 u32 bank = GPIO_BANK(pin); local
65 struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
dram_sun6i.c 333 int bank, bus, columns; local
398 /* Detect bank size */
400 bank = mctl_mem_matches(offset) ? 0 : 1;
402 /* Restore interleave, chan and rank values, set bank size */
406 MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
409 return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);
  /external/u-boot/cmd/
fuse.c 47 u32 bank, word, cnt, val; local
53 if (argc < 2 || strtou32(argv[0], 0, &bank) ||
63 printf("Reading bank %u:\n", bank);
68 ret = fuse_read(bank, word, &val);
81 printf("Sensing bank %u:\n", bank);
86 ret = fuse_sense(bank, word, &val);
101 printf("Programming bank %u word 0x%.8x to 0x%.8x...\n",
102 bank, word, val)
    [all...]
  /external/u-boot/drivers/gpio/
hi6220_gpio.c 15 struct gpio_bank *bank = dev_get_priv(dev); local
18 data = readb(bank->base + HI6220_GPIO_DIR);
20 writeb(data, bank->base + HI6220_GPIO_DIR);
28 struct gpio_bank *bank = dev_get_priv(dev); local
30 writeb(!!value << gpio, bank->base + (BIT(gpio + 2)));
37 struct gpio_bank *bank = dev_get_priv(dev); local
40 data = readb(bank->base + HI6220_GPIO_DIR);
42 writeb(data, bank->base + HI6220_GPIO_DIR);
51 struct gpio_bank *bank = dev_get_priv(dev); local
53 return !!readb(bank->base + (BIT(gpio + 2)))
67 struct gpio_bank *bank = dev_get_priv(dev); local
    [all...]
74x164_gpio.c 65 uint bank = priv->nregs - 1 - offset / 8; local
68 return (priv->buffer[bank] >> pin) & 0x1;
75 uint bank = priv->nregs - 1 - offset / 8; local
80 priv->buffer[bank] |= 1 << pin;
82 priv->buffer[bank] &= ~(1 << pin);
gpio-uniphier.c 25 static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
29 reg = (bank + 1) * 8;
42 unsigned int *bank, u32 *mask)
44 *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
59 static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
67 uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
74 unsigned int bank; local
77 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
79 uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
86 unsigned int bank, reg_offset local
    [all...]
intel_broadwell_gpio.c 26 * @bank: Bank number for this bank (0, 1 or 2)
27 * @offset: GPIO offset for this bank (0, 32 or 64)
31 int bank; member in struct:broadwell_bank_priv
47 debug("%s: request bank %d offset %d: ", __func__, priv->bank, offset);
48 val = inl(&regs->own[priv->bank]);
109 if (!(inl(&regs->own[priv->bank]) & mask))
133 priv->bank = plat->bank
145 int bank; local
    [all...]
mxs_gpio.c 56 uint32_t bank = PAD_BANK(gpio); local
57 uint32_t offset = PINCTRL_DIN(bank);
66 uint32_t bank = PAD_BANK(gpio); local
67 uint32_t offset = PINCTRL_DOUT(bank);
79 uint32_t bank = PAD_BANK(gpio); local
80 uint32_t offset = PINCTRL_DOE(bank);
91 uint32_t bank = PAD_BANK(gpio); local
92 uint32_t offset = PINCTRL_DOE(bank);
118 unsigned bank, pin; local
121 bank = simple_strtoul(name, &end, 10)
    [all...]
rk_gpio.c 28 int bank; member in struct:rockchip_gpio_priv
85 ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
108 priv->bank = trailing_strtoln(dev->name, end);
109 priv->name[0] = 'A' + priv->bank;
124 { .compatible = "rockchip,gpio-bank" },
  /external/u-boot/drivers/mtd/
stm32_flash.c 82 u8 bank = 0xFF; local
87 bank = i;
91 if (bank == 0xFF)
103 if (bank == 0) {
106 } else if (bank == 1) {
  /external/u-boot/drivers/reset/
reset-meson.c 38 uint bank = reset_ctl->id / BITS_PER_REG; local
40 uint reg_offset = LEVEL_OFFSET + (bank << 2);
reset-rockchip.c 50 int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG; local
55 priv->base + (bank * 4));
57 rk_setreg(priv->base + (bank * 4), BIT(offset));
65 int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG; local
70 priv->base + (bank * 4));
72 rk_clrreg(priv->base + (bank * 4), BIT(offset));
reset-socfpga.c 35 int bank = id / (reg_width * BITS_PER_BYTE); local
38 setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
47 int bank = id / (reg_width * BITS_PER_BYTE); local
50 clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
stm32-reset.c 38 int bank = (reset_ctl->id / BITS_PER_LONG) * 4; local
40 debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
41 reset_ctl->id, bank, offset);
45 writel(BIT(offset), priv->base + bank);
47 setbits_le32(priv->base + bank, BIT(offset));
55 int bank = (reset_ctl->id / BITS_PER_LONG) * 4; local
57 debug("%s: reset id = %ld bank = %d offset = %d)\n", __func__,
58 reset_ctl->id, bank, offset);
62 writel(BIT(offset), priv->base + bank + RCC_CL);
64 clrbits_le32(priv->base + bank, BIT(offset))
    [all...]
  /external/speex/libspeexdsp/
filterbank.c 56 FilterBank *bank; local
66 bank = (FilterBank*)speex_alloc(sizeof(FilterBank));
67 bank->nb_banks = banks;
68 bank->len = len;
69 bank->bank_left = (int*)speex_alloc(len*sizeof(int));
70 bank->bank_right = (int*)speex_alloc(len*sizeof(int));
71 bank->filter_left = (spx_word16_t*)speex_alloc(len*sizeof(spx_word16_t));
72 bank->filter_right = (spx_word16_t*)speex_alloc(len*sizeof(spx_word16_t));
75 bank->scaling = (float*)speex_alloc(banks*sizeof(float));
99 bank->bank_left[i] = id1
    [all...]
  /external/u-boot/arch/arm/mach-exynos/include/mach/
sromc.h 33 /* Configure the Band Width and Bank Control Regs for required SROMC Bank */
49 u8 bank; /* srom bank number */ member in struct:fdt_sromc
  /external/u-boot/arch/arm/mach-imx/mx7/
soc.c 96 .bank = 1,
104 struct fuse_bank *bank = &ocotp->bank[1]; local
106 (struct fuse_bank1_regs *)bank->fuse_regs;
230 struct fuse_bank *bank = &ocotp->bank[0]; local
232 (struct fuse_bank0_regs *)bank->fuse_regs;
  /external/u-boot/arch/x86/cpu/tangier/
sdram.c 150 int bank = 0; local
161 gd->bd->bi_dram[bank].start = mentry->phys_start;
162 gd->bd->bi_dram[bank].size = mentry->pages << 12;
163 bank++;
166 return bank;
  /external/u-boot/arch/x86/lib/
bootm.c 54 int bank; local
58 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
59 start[bank] = bd->bi_dram[bank].start;
60 size[bank] = bd->bi_dram[bank].size;
  /external/u-boot/arch/xtensa/include/asm/
bootparam.h 49 struct meminfo bank[0]; member in struct:sysmem_info
  /external/u-boot/drivers/pinctrl/exynos/
pinctrl-exynos.c 43 char bank[10]; local
46 * The format of the pin name is <bank name>-<pin_number>.
47 * Example: gpa0-4 (gpa0 is the bank name and 4 is the pin number.
50 bank[idx] = pin_name[idx];
53 bank[idx] = '\0';
56 /* lookup the pin bank data using the pin bank name */
58 if (!strcmp(bank, bank_data[idx].name))
  /external/u-boot/drivers/pinctrl/
pinctrl-at91-pio4.c 95 u32 bank)
100 ATMEL_PIO_BANK_OFFSET * bank);
112 u32 offset, func, bank, line; local
136 bank = ATMEL_PIO_BANK(offset);
139 bank_base = atmel_pio4_bank_base(dev, bank);
  /bionic/libc/kernel/uapi/asm-x86/asm/
mce.h 37 __u8 bank; member in struct:mce

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