1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010 Samsung Electronics 4 * Naveen Krishna Ch <ch.naveen (at) samsung.com> 5 * 6 * Note: This file contains the register description for SROMC 7 */ 8 9 #ifndef __ASM_ARCH_SROMC_H_ 10 #define __ASM_ARCH_SROMC_H_ 11 12 #define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) 13 #define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ 14 /* 1-> Byte base address*/ 15 #define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) 16 #define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) 17 18 #define SROMC_BC_TACS(x) (x << 28) /* address set-up */ 19 #define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ 20 #define SROMC_BC_TACC(x) (x << 16) /* access cycle */ 21 #define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ 22 #define SROMC_BC_TAH(x) (x << 8) /* address holding time */ 23 #define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ 24 #define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ 25 26 #ifndef __ASSEMBLY__ 27 struct s5p_sromc { 28 unsigned int bw; 29 unsigned int bc[4]; 30 }; 31 #endif /* __ASSEMBLY__ */ 32 33 /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ 34 void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); 35 36 enum { 37 FDT_SROM_PMC, 38 FDT_SROM_TACP, 39 FDT_SROM_TAH, 40 FDT_SROM_TCOH, 41 FDT_SROM_TACC, 42 FDT_SROM_TCOS, 43 FDT_SROM_TACS, 44 45 FDT_SROM_TIMING_COUNT, 46 }; 47 48 struct fdt_sromc { 49 u8 bank; /* srom bank number */ 50 u8 width; /* bus width in bytes */ 51 unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ 52 }; 53 54 #endif /* __ASM_ARCH_SROMC_H_ */ 55
