1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015, Bin Meng <bmeng.cn (at) gmail.com> 4 */ 5 6 #ifndef _QUARK_H_ 7 #define _QUARK_H_ 8 9 /* Message Bus Ports */ 10 #define MSG_PORT_MEM_ARBITER 0x00 11 #define MSG_PORT_HOST_BRIDGE 0x03 12 #define MSG_PORT_RMU 0x04 13 #define MSG_PORT_MEM_MGR 0x05 14 #define MSG_PORT_USB_AFE 0x14 15 #define MSG_PORT_PCIE_AFE 0x16 16 #define MSG_PORT_SOC_UNIT 0x31 17 18 /* Port 0x00: Memory Arbiter Message Port Registers */ 19 20 /* Enhanced Configuration Space */ 21 #define AEC_CTRL 0x00 22 23 /* Port 0x03: Host Bridge Message Port Registers */ 24 25 /* Host Miscellaneous Controls 2 */ 26 #define HMISC2 0x03 27 28 #define HMISC2_SEGE 0x00000002 29 #define HMISC2_SEGF 0x00000004 30 #define HMISC2_SEGAB 0x00000010 31 32 /* Host Memory I/O Boundary */ 33 #define HM_BOUND 0x08 34 #define HM_BOUND_LOCK 0x00000001 35 36 /* Extended Configuration Space */ 37 #define HEC_REG 0x09 38 39 /* MTRR Registers */ 40 #define MTRR_CAP 0x40 41 #define MTRR_DEF_TYPE 0x41 42 43 #define MTRR_FIX_64K_00000 0x42 44 #define MTRR_FIX_64K_40000 0x43 45 #define MTRR_FIX_16K_80000 0x44 46 #define MTRR_FIX_16K_90000 0x45 47 #define MTRR_FIX_16K_A0000 0x46 48 #define MTRR_FIX_16K_B0000 0x47 49 #define MTRR_FIX_4K_C0000 0x48 50 #define MTRR_FIX_4K_C4000 0x49 51 #define MTRR_FIX_4K_C8000 0x4a 52 #define MTRR_FIX_4K_CC000 0x4b 53 #define MTRR_FIX_4K_D0000 0x4c 54 #define MTRR_FIX_4K_D4000 0x4d 55 #define MTRR_FIX_4K_D8000 0x4e 56 #define MTRR_FIX_4K_DC000 0x4f 57 #define MTRR_FIX_4K_E0000 0x50 58 #define MTRR_FIX_4K_E4000 0x51 59 #define MTRR_FIX_4K_E8000 0x52 60 #define MTRR_FIX_4K_EC000 0x53 61 #define MTRR_FIX_4K_F0000 0x54 62 #define MTRR_FIX_4K_F4000 0x55 63 #define MTRR_FIX_4K_F8000 0x56 64 #define MTRR_FIX_4K_FC000 0x57 65 66 #define MTRR_SMRR_PHYBASE 0x58 67 #define MTRR_SMRR_PHYMASK 0x59 68 69 #define MTRR_VAR_PHYBASE(n) (0x5a + 2 * (n)) 70 #define MTRR_VAR_PHYMASK(n) (0x5b + 2 * (n)) 71 72 #ifndef __ASSEMBLY__ 73 74 /* variable range MTRR usage */ 75 enum { 76 MTRR_VAR_ROM, 77 MTRR_VAR_ESRAM, 78 MTRR_VAR_RAM 79 }; 80 81 #endif /* __ASSEMBLY__ */ 82 83 /* Port 0x04: Remote Management Unit Message Port Registers */ 84 85 /* ACPI PBLK Base Address Register */ 86 #define PBLK_BA 0x70 87 88 /* Control Register */ 89 #define RMU_CTRL 0x71 90 91 /* SPI DMA Base Address Register */ 92 #define SPI_DMA_BA 0x7a 93 94 /* Thermal Sensor Register */ 95 #define TS_MODE 0xb0 96 #define TS_TEMP 0xb1 97 #define TS_TRIP 0xb2 98 99 /* Port 0x05: Memory Manager Message Port Registers */ 100 101 /* eSRAM Block Page Control */ 102 #define ESRAM_BLK_CTRL 0x82 103 #define ESRAM_BLOCK_MODE 0x10000000 104 105 /* Port 0x14: USB2 AFE Unit Port Registers */ 106 107 #define USB2_GLOBAL_PORT 0x4001 108 #define USB2_PLL1 0x7f02 109 #define USB2_PLL2 0x7f03 110 #define USB2_COMPBG 0x7f04 111 112 /* Port 0x16: PCIe AFE Unit Port Registers */ 113 114 #define PCIE_RXPICTRL0_L0 0x2080 115 #define PCIE_RXPICTRL0_L1 0x2180 116 117 /* Port 0x31: SoC Unit Port Registers */ 118 119 /* Thermal Sensor Config */ 120 #define TS_CFG1 0x31 121 #define TS_CFG2 0x32 122 #define TS_CFG3 0x33 123 #define TS_CFG4 0x34 124 125 /* PCIe Controller Config */ 126 #define PCIE_CFG 0x36 127 #define PCIE_CTLR_PRI_RST 0x00010000 128 #define PCIE_PHY_SB_RST 0x00020000 129 #define PCIE_CTLR_SB_RST 0x00040000 130 #define PCIE_PHY_LANE_RST 0x00090000 131 #define PCIE_CTLR_MAIN_RST 0x00100000 132 133 /* DRAM */ 134 #define DRAM_BASE 0x00000000 135 #define DRAM_MAX_SIZE 0x80000000 136 137 /* eSRAM */ 138 #define ESRAM_SIZE 0x80000 139 140 /* Memory BAR Enable */ 141 #define MEM_BAR_EN 0x00000001 142 143 /* I/O BAR Enable */ 144 #define IO_BAR_EN 0x80000000 145 146 /* 64KiB of RMU binary in flash */ 147 #define RMU_BINARY_SIZE 0x10000 148 149 /* PCIe Root Port Configuration Registers */ 150 151 #define PCIE_RP_CCFG 0xd0 152 #define CCFG_UPRS (1 << 14) 153 #define CCFG_UNRS (1 << 15) 154 #define CCFG_UNSD (1 << 23) 155 #define CCFG_UPSD (1 << 24) 156 157 #define PCIE_RP_MPC2 0xd4 158 #define MPC2_IPF (1 << 11) 159 160 #define PCIE_RP_MBC 0xf4 161 #define MBC_SBIC (3 << 16) 162 163 /* Legacy Bridge PCI Configuration Registers */ 164 #define LB_GBA 0x44 165 #define LB_PM1BLK 0x48 166 #define LB_GPE0BLK 0x4c 167 #define LB_ACTL 0x58 168 #define LB_PABCDRC 0x60 169 #define LB_PEFGHRC 0x64 170 #define LB_WDTBA 0x84 171 #define LB_BCE 0xd4 172 #define LB_BC 0xd8 173 #define LB_RCBA 0xf0 174 175 /* USB EHCI memory-mapped registers */ 176 #define EHCI_INSNREG01 0x94 177 178 /* USB device memory-mapped registers */ 179 #define USBD_INT_MASK 0x410 180 #define USBD_EP_INT_STS 0x414 181 #define USBD_EP_INT_MASK 0x418 182 183 #ifndef __ASSEMBLY__ 184 185 /* Root Complex Register Block */ 186 struct quark_rcba { 187 u32 rctl; 188 u32 esd; 189 u32 rsvd1[3150]; 190 u16 rmu_ir; 191 u16 d23_ir; 192 u16 core_ir; 193 u16 d20d21_ir; 194 }; 195 196 #include <asm/io.h> 197 #include <asm/pci.h> 198 199 /** 200 * qrk_pci_read_config_dword() - Read a configuration value 201 * 202 * @dev: PCI device address: bus, device and function 203 * @offset: Dword offset within the device's configuration space 204 * @valuep: Place to put the returned value 205 * 206 * Note: This routine is inlined to provide better performance on Quark 207 */ 208 static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset, 209 u32 *valuep) 210 { 211 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); 212 *valuep = inl(PCI_REG_DATA); 213 } 214 215 /** 216 * qrk_pci_write_config_dword() - Write a PCI configuration value 217 * 218 * @dev: PCI device address: bus, device and function 219 * @offset: Dword offset within the device's configuration space 220 * @value: Value to write 221 * 222 * Note: This routine is inlined to provide better performance on Quark 223 */ 224 static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset, 225 u32 value) 226 { 227 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); 228 outl(value, PCI_REG_DATA); 229 } 230 231 /** 232 * board_assert_perst() - Assert the PERST# pin 233 * 234 * The CPU interface to the PERST# signal on Quark is platform dependent. 235 * Board-specific codes need supply this routine to assert PCIe slot reset. 236 * 237 * The tricky part in this routine is that any APIs that may trigger PCI 238 * enumeration process are strictly forbidden, as any access to PCIe root 239 * port's configuration registers will cause system hang while it is held 240 * in reset. 241 */ 242 void board_assert_perst(void); 243 244 /** 245 * board_deassert_perst() - De-assert the PERST# pin 246 * 247 * The CPU interface to the PERST# signal on Quark is platform dependent. 248 * Board-specific codes need supply this routine to de-assert PCIe slot reset. 249 * 250 * The tricky part in this routine is that any APIs that may trigger PCI 251 * enumeration process are strictly forbidden, as any access to PCIe root 252 * port's configuration registers will cause system hang while it is held 253 * in reset. 254 */ 255 void board_deassert_perst(void); 256 257 #endif /* __ASSEMBLY__ */ 258 259 #endif /* _QUARK_H_ */ 260
