1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file Methods common to all machine operands. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/MachineOperand.h" 15 #include "llvm/ADT/StringExtras.h" 16 #include "llvm/Analysis/Loads.h" 17 #include "llvm/CodeGen/MIRPrinter.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineJumpTableInfo.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/TargetInstrInfo.h" 22 #include "llvm/CodeGen/TargetRegisterInfo.h" 23 #include "llvm/Config/llvm-config.h" 24 #include "llvm/IR/Constants.h" 25 #include "llvm/IR/IRPrintingPasses.h" 26 #include "llvm/IR/ModuleSlotTracker.h" 27 #include "llvm/Target/TargetIntrinsicInfo.h" 28 #include "llvm/Target/TargetMachine.h" 29 30 using namespace llvm; 31 32 static cl::opt<int> 33 PrintRegMaskNumRegs("print-regmask-num-regs", 34 cl::desc("Number of registers to limit to when " 35 "printing regmask operands in IR dumps. " 36 "unlimited = -1"), 37 cl::init(32), cl::Hidden); 38 39 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) { 40 if (const MachineInstr *MI = MO.getParent()) 41 if (const MachineBasicBlock *MBB = MI->getParent()) 42 if (const MachineFunction *MF = MBB->getParent()) 43 return MF; 44 return nullptr; 45 } 46 static MachineFunction *getMFIfAvailable(MachineOperand &MO) { 47 return const_cast<MachineFunction *>( 48 getMFIfAvailable(const_cast<const MachineOperand &>(MO))); 49 } 50 51 void MachineOperand::setReg(unsigned Reg) { 52 if (getReg() == Reg) 53 return; // No change. 54 55 // Clear the IsRenamable bit to keep it conservatively correct. 56 IsRenamable = false; 57 58 // Otherwise, we have to change the register. If this operand is embedded 59 // into a machine function, we need to update the old and new register's 60 // use/def lists. 61 if (MachineFunction *MF = getMFIfAvailable(*this)) { 62 MachineRegisterInfo &MRI = MF->getRegInfo(); 63 MRI.removeRegOperandFromUseList(this); 64 SmallContents.RegNo = Reg; 65 MRI.addRegOperandToUseList(this); 66 return; 67 } 68 69 // Otherwise, just change the register, no problem. :) 70 SmallContents.RegNo = Reg; 71 } 72 73 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, 74 const TargetRegisterInfo &TRI) { 75 assert(TargetRegisterInfo::isVirtualRegister(Reg)); 76 if (SubIdx && getSubReg()) 77 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 78 setReg(Reg); 79 if (SubIdx) 80 setSubReg(SubIdx); 81 } 82 83 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { 84 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 85 if (getSubReg()) { 86 Reg = TRI.getSubReg(Reg, getSubReg()); 87 // Note that getSubReg() may return 0 if the sub-register doesn't exist. 88 // That won't happen in legal code. 89 setSubReg(0); 90 if (isDef()) 91 setIsUndef(false); 92 } 93 setReg(Reg); 94 } 95 96 /// Change a def to a use, or a use to a def. 97 void MachineOperand::setIsDef(bool Val) { 98 assert(isReg() && "Wrong MachineOperand accessor"); 99 assert((!Val || !isDebug()) && "Marking a debug operation as def"); 100 if (IsDef == Val) 101 return; 102 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported"); 103 // MRI may keep uses and defs in different list positions. 104 if (MachineFunction *MF = getMFIfAvailable(*this)) { 105 MachineRegisterInfo &MRI = MF->getRegInfo(); 106 MRI.removeRegOperandFromUseList(this); 107 IsDef = Val; 108 MRI.addRegOperandToUseList(this); 109 return; 110 } 111 IsDef = Val; 112 } 113 114 bool MachineOperand::isRenamable() const { 115 assert(isReg() && "Wrong MachineOperand accessor"); 116 assert(TargetRegisterInfo::isPhysicalRegister(getReg()) && 117 "isRenamable should only be checked on physical registers"); 118 if (!IsRenamable) 119 return false; 120 121 const MachineInstr *MI = getParent(); 122 if (!MI) 123 return true; 124 125 if (isDef()) 126 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle); 127 128 assert(isUse() && "Reg is not def or use"); 129 return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle); 130 } 131 132 void MachineOperand::setIsRenamable(bool Val) { 133 assert(isReg() && "Wrong MachineOperand accessor"); 134 assert(TargetRegisterInfo::isPhysicalRegister(getReg()) && 135 "setIsRenamable should only be called on physical registers"); 136 IsRenamable = Val; 137 } 138 139 // If this operand is currently a register operand, and if this is in a 140 // function, deregister the operand from the register's use/def list. 141 void MachineOperand::removeRegFromUses() { 142 if (!isReg() || !isOnRegUseList()) 143 return; 144 145 if (MachineFunction *MF = getMFIfAvailable(*this)) 146 MF->getRegInfo().removeRegOperandFromUseList(this); 147 } 148 149 /// ChangeToImmediate - Replace this operand with a new immediate operand of 150 /// the specified value. If an operand is known to be an immediate already, 151 /// the setImm method should be used. 152 void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 153 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); 154 155 removeRegFromUses(); 156 157 OpKind = MO_Immediate; 158 Contents.ImmVal = ImmVal; 159 } 160 161 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) { 162 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); 163 164 removeRegFromUses(); 165 166 OpKind = MO_FPImmediate; 167 Contents.CFP = FPImm; 168 } 169 170 void MachineOperand::ChangeToES(const char *SymName, 171 unsigned char TargetFlags) { 172 assert((!isReg() || !isTied()) && 173 "Cannot change a tied operand into an external symbol"); 174 175 removeRegFromUses(); 176 177 OpKind = MO_ExternalSymbol; 178 Contents.OffsetedInfo.Val.SymbolName = SymName; 179 setOffset(0); // Offset is always 0. 180 setTargetFlags(TargetFlags); 181 } 182 183 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) { 184 assert((!isReg() || !isTied()) && 185 "Cannot change a tied operand into an MCSymbol"); 186 187 removeRegFromUses(); 188 189 OpKind = MO_MCSymbol; 190 Contents.Sym = Sym; 191 } 192 193 void MachineOperand::ChangeToFrameIndex(int Idx) { 194 assert((!isReg() || !isTied()) && 195 "Cannot change a tied operand into a FrameIndex"); 196 197 removeRegFromUses(); 198 199 OpKind = MO_FrameIndex; 200 setIndex(Idx); 201 } 202 203 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset, 204 unsigned char TargetFlags) { 205 assert((!isReg() || !isTied()) && 206 "Cannot change a tied operand into a FrameIndex"); 207 208 removeRegFromUses(); 209 210 OpKind = MO_TargetIndex; 211 setIndex(Idx); 212 setOffset(Offset); 213 setTargetFlags(TargetFlags); 214 } 215 216 /// ChangeToRegister - Replace this operand with a new register operand of 217 /// the specified value. If an operand is known to be an register already, 218 /// the setReg method should be used. 219 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 220 bool isKill, bool isDead, bool isUndef, 221 bool isDebug) { 222 MachineRegisterInfo *RegInfo = nullptr; 223 if (MachineFunction *MF = getMFIfAvailable(*this)) 224 RegInfo = &MF->getRegInfo(); 225 // If this operand is already a register operand, remove it from the 226 // register's use/def lists. 227 bool WasReg = isReg(); 228 if (RegInfo && WasReg) 229 RegInfo->removeRegOperandFromUseList(this); 230 231 // Change this to a register and set the reg#. 232 assert(!(isDead && !isDef) && "Dead flag on non-def"); 233 assert(!(isKill && isDef) && "Kill flag on def"); 234 OpKind = MO_Register; 235 SmallContents.RegNo = Reg; 236 SubReg_TargetFlags = 0; 237 IsDef = isDef; 238 IsImp = isImp; 239 IsDeadOrKill = isKill | isDead; 240 IsRenamable = false; 241 IsUndef = isUndef; 242 IsInternalRead = false; 243 IsEarlyClobber = false; 244 IsDebug = isDebug; 245 // Ensure isOnRegUseList() returns false. 246 Contents.Reg.Prev = nullptr; 247 // Preserve the tie when the operand was already a register. 248 if (!WasReg) 249 TiedTo = 0; 250 251 // If this operand is embedded in a function, add the operand to the 252 // register's use/def list. 253 if (RegInfo) 254 RegInfo->addRegOperandToUseList(this); 255 } 256 257 /// isIdenticalTo - Return true if this operand is identical to the specified 258 /// operand. Note that this should stay in sync with the hash_value overload 259 /// below. 260 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 261 if (getType() != Other.getType() || 262 getTargetFlags() != Other.getTargetFlags()) 263 return false; 264 265 switch (getType()) { 266 case MachineOperand::MO_Register: 267 return getReg() == Other.getReg() && isDef() == Other.isDef() && 268 getSubReg() == Other.getSubReg(); 269 case MachineOperand::MO_Immediate: 270 return getImm() == Other.getImm(); 271 case MachineOperand::MO_CImmediate: 272 return getCImm() == Other.getCImm(); 273 case MachineOperand::MO_FPImmediate: 274 return getFPImm() == Other.getFPImm(); 275 case MachineOperand::MO_MachineBasicBlock: 276 return getMBB() == Other.getMBB(); 277 case MachineOperand::MO_FrameIndex: 278 return getIndex() == Other.getIndex(); 279 case MachineOperand::MO_ConstantPoolIndex: 280 case MachineOperand::MO_TargetIndex: 281 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 282 case MachineOperand::MO_JumpTableIndex: 283 return getIndex() == Other.getIndex(); 284 case MachineOperand::MO_GlobalAddress: 285 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 286 case MachineOperand::MO_ExternalSymbol: 287 return strcmp(getSymbolName(), Other.getSymbolName()) == 0 && 288 getOffset() == Other.getOffset(); 289 case MachineOperand::MO_BlockAddress: 290 return getBlockAddress() == Other.getBlockAddress() && 291 getOffset() == Other.getOffset(); 292 case MachineOperand::MO_RegisterMask: 293 case MachineOperand::MO_RegisterLiveOut: { 294 // Shallow compare of the two RegMasks 295 const uint32_t *RegMask = getRegMask(); 296 const uint32_t *OtherRegMask = Other.getRegMask(); 297 if (RegMask == OtherRegMask) 298 return true; 299 300 if (const MachineFunction *MF = getMFIfAvailable(*this)) { 301 // Calculate the size of the RegMask 302 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 303 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32; 304 305 // Deep compare of the two RegMasks 306 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask); 307 } 308 // We don't know the size of the RegMask, so we can't deep compare the two 309 // reg masks. 310 return false; 311 } 312 case MachineOperand::MO_MCSymbol: 313 return getMCSymbol() == Other.getMCSymbol(); 314 case MachineOperand::MO_CFIIndex: 315 return getCFIIndex() == Other.getCFIIndex(); 316 case MachineOperand::MO_Metadata: 317 return getMetadata() == Other.getMetadata(); 318 case MachineOperand::MO_IntrinsicID: 319 return getIntrinsicID() == Other.getIntrinsicID(); 320 case MachineOperand::MO_Predicate: 321 return getPredicate() == Other.getPredicate(); 322 } 323 llvm_unreachable("Invalid machine operand type"); 324 } 325 326 // Note: this must stay exactly in sync with isIdenticalTo above. 327 hash_code llvm::hash_value(const MachineOperand &MO) { 328 switch (MO.getType()) { 329 case MachineOperand::MO_Register: 330 // Register operands don't have target flags. 331 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); 332 case MachineOperand::MO_Immediate: 333 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm()); 334 case MachineOperand::MO_CImmediate: 335 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm()); 336 case MachineOperand::MO_FPImmediate: 337 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm()); 338 case MachineOperand::MO_MachineBasicBlock: 339 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB()); 340 case MachineOperand::MO_FrameIndex: 341 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 342 case MachineOperand::MO_ConstantPoolIndex: 343 case MachineOperand::MO_TargetIndex: 344 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(), 345 MO.getOffset()); 346 case MachineOperand::MO_JumpTableIndex: 347 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 348 case MachineOperand::MO_ExternalSymbol: 349 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(), 350 MO.getSymbolName()); 351 case MachineOperand::MO_GlobalAddress: 352 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(), 353 MO.getOffset()); 354 case MachineOperand::MO_BlockAddress: 355 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(), 356 MO.getOffset()); 357 case MachineOperand::MO_RegisterMask: 358 case MachineOperand::MO_RegisterLiveOut: 359 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask()); 360 case MachineOperand::MO_Metadata: 361 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata()); 362 case MachineOperand::MO_MCSymbol: 363 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol()); 364 case MachineOperand::MO_CFIIndex: 365 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex()); 366 case MachineOperand::MO_IntrinsicID: 367 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID()); 368 case MachineOperand::MO_Predicate: 369 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate()); 370 } 371 llvm_unreachable("Invalid machine operand type"); 372 } 373 374 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from 375 // it. 376 static void tryToGetTargetInfo(const MachineOperand &MO, 377 const TargetRegisterInfo *&TRI, 378 const TargetIntrinsicInfo *&IntrinsicInfo) { 379 if (const MachineFunction *MF = getMFIfAvailable(MO)) { 380 TRI = MF->getSubtarget().getRegisterInfo(); 381 IntrinsicInfo = MF->getTarget().getIntrinsicInfo(); 382 } 383 } 384 385 static const char *getTargetIndexName(const MachineFunction &MF, int Index) { 386 const auto *TII = MF.getSubtarget().getInstrInfo(); 387 assert(TII && "expected instruction info"); 388 auto Indices = TII->getSerializableTargetIndices(); 389 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) { 390 return I.first == Index; 391 }); 392 if (Found != Indices.end()) 393 return Found->second; 394 return nullptr; 395 } 396 397 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) { 398 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags(); 399 for (const auto &I : Flags) { 400 if (I.first == TF) { 401 return I.second; 402 } 403 } 404 return nullptr; 405 } 406 407 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS, 408 const TargetRegisterInfo *TRI) { 409 if (!TRI) { 410 OS << "%dwarfreg." << DwarfReg; 411 return; 412 } 413 414 int Reg = TRI->getLLVMRegNum(DwarfReg, true); 415 if (Reg == -1) { 416 OS << "<badreg>"; 417 return; 418 } 419 OS << printReg(Reg, TRI); 420 } 421 422 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB, 423 ModuleSlotTracker &MST) { 424 OS << "%ir-block."; 425 if (BB.hasName()) { 426 printLLVMNameWithoutPrefix(OS, BB.getName()); 427 return; 428 } 429 Optional<int> Slot; 430 if (const Function *F = BB.getParent()) { 431 if (F == MST.getCurrentFunction()) { 432 Slot = MST.getLocalSlot(&BB); 433 } else if (const Module *M = F->getParent()) { 434 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false); 435 CustomMST.incorporateFunction(*F); 436 Slot = CustomMST.getLocalSlot(&BB); 437 } 438 } 439 if (Slot) 440 MachineOperand::printIRSlotNumber(OS, *Slot); 441 else 442 OS << "<unknown>"; 443 } 444 445 static void printIRValueReference(raw_ostream &OS, const Value &V, 446 ModuleSlotTracker &MST) { 447 if (isa<GlobalValue>(V)) { 448 V.printAsOperand(OS, /*PrintType=*/false, MST); 449 return; 450 } 451 if (isa<Constant>(V)) { 452 // Machine memory operands can load/store to/from constant value pointers. 453 OS << '`'; 454 V.printAsOperand(OS, /*PrintType=*/true, MST); 455 OS << '`'; 456 return; 457 } 458 OS << "%ir."; 459 if (V.hasName()) { 460 printLLVMNameWithoutPrefix(OS, V.getName()); 461 return; 462 } 463 MachineOperand::printIRSlotNumber(OS, MST.getLocalSlot(&V)); 464 } 465 466 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context, 467 SyncScope::ID SSID, 468 SmallVectorImpl<StringRef> &SSNs) { 469 switch (SSID) { 470 case SyncScope::System: 471 break; 472 default: 473 if (SSNs.empty()) 474 Context.getSyncScopeNames(SSNs); 475 476 OS << "syncscope(\""; 477 printEscapedString(SSNs[SSID], OS); 478 OS << "\") "; 479 break; 480 } 481 } 482 483 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII, 484 unsigned TMMOFlag) { 485 auto Flags = TII.getSerializableMachineMemOperandTargetFlags(); 486 for (const auto &I : Flags) { 487 if (I.first == TMMOFlag) { 488 return I.second; 489 } 490 } 491 return nullptr; 492 } 493 494 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed, 495 const MachineFrameInfo *MFI) { 496 StringRef Name; 497 if (MFI) { 498 IsFixed = MFI->isFixedObjectIndex(FrameIndex); 499 if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex)) 500 if (Alloca->hasName()) 501 Name = Alloca->getName(); 502 if (IsFixed) 503 FrameIndex -= MFI->getObjectIndexBegin(); 504 } 505 MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name); 506 } 507 508 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index, 509 const TargetRegisterInfo *TRI) { 510 OS << "%subreg."; 511 if (TRI) 512 OS << TRI->getSubRegIndexName(Index); 513 else 514 OS << Index; 515 } 516 517 void MachineOperand::printTargetFlags(raw_ostream &OS, 518 const MachineOperand &Op) { 519 if (!Op.getTargetFlags()) 520 return; 521 const MachineFunction *MF = getMFIfAvailable(Op); 522 if (!MF) 523 return; 524 525 const auto *TII = MF->getSubtarget().getInstrInfo(); 526 assert(TII && "expected instruction info"); 527 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags()); 528 OS << "target-flags("; 529 const bool HasDirectFlags = Flags.first; 530 const bool HasBitmaskFlags = Flags.second; 531 if (!HasDirectFlags && !HasBitmaskFlags) { 532 OS << "<unknown>) "; 533 return; 534 } 535 if (HasDirectFlags) { 536 if (const auto *Name = getTargetFlagName(TII, Flags.first)) 537 OS << Name; 538 else 539 OS << "<unknown target flag>"; 540 } 541 if (!HasBitmaskFlags) { 542 OS << ") "; 543 return; 544 } 545 bool IsCommaNeeded = HasDirectFlags; 546 unsigned BitMask = Flags.second; 547 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags(); 548 for (const auto &Mask : BitMasks) { 549 // Check if the flag's bitmask has the bits of the current mask set. 550 if ((BitMask & Mask.first) == Mask.first) { 551 if (IsCommaNeeded) 552 OS << ", "; 553 IsCommaNeeded = true; 554 OS << Mask.second; 555 // Clear the bits which were serialized from the flag's bitmask. 556 BitMask &= ~(Mask.first); 557 } 558 } 559 if (BitMask) { 560 // When the resulting flag's bitmask isn't zero, we know that we didn't 561 // serialize all of the bit flags. 562 if (IsCommaNeeded) 563 OS << ", "; 564 OS << "<unknown bitmask target flag>"; 565 } 566 OS << ") "; 567 } 568 569 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) { 570 OS << "<mcsymbol " << Sym << ">"; 571 } 572 573 void MachineOperand::printStackObjectReference(raw_ostream &OS, 574 unsigned FrameIndex, 575 bool IsFixed, StringRef Name) { 576 if (IsFixed) { 577 OS << "%fixed-stack." << FrameIndex; 578 return; 579 } 580 581 OS << "%stack." << FrameIndex; 582 if (!Name.empty()) 583 OS << '.' << Name; 584 } 585 586 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) { 587 if (Offset == 0) 588 return; 589 if (Offset < 0) { 590 OS << " - " << -Offset; 591 return; 592 } 593 OS << " + " << Offset; 594 } 595 596 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) { 597 if (Slot == -1) 598 OS << "<badref>"; 599 else 600 OS << Slot; 601 } 602 603 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI, 604 const TargetRegisterInfo *TRI) { 605 switch (CFI.getOperation()) { 606 case MCCFIInstruction::OpSameValue: 607 OS << "same_value "; 608 if (MCSymbol *Label = CFI.getLabel()) 609 MachineOperand::printSymbol(OS, *Label); 610 printCFIRegister(CFI.getRegister(), OS, TRI); 611 break; 612 case MCCFIInstruction::OpRememberState: 613 OS << "remember_state "; 614 if (MCSymbol *Label = CFI.getLabel()) 615 MachineOperand::printSymbol(OS, *Label); 616 break; 617 case MCCFIInstruction::OpRestoreState: 618 OS << "restore_state "; 619 if (MCSymbol *Label = CFI.getLabel()) 620 MachineOperand::printSymbol(OS, *Label); 621 break; 622 case MCCFIInstruction::OpOffset: 623 OS << "offset "; 624 if (MCSymbol *Label = CFI.getLabel()) 625 MachineOperand::printSymbol(OS, *Label); 626 printCFIRegister(CFI.getRegister(), OS, TRI); 627 OS << ", " << CFI.getOffset(); 628 break; 629 case MCCFIInstruction::OpDefCfaRegister: 630 OS << "def_cfa_register "; 631 if (MCSymbol *Label = CFI.getLabel()) 632 MachineOperand::printSymbol(OS, *Label); 633 printCFIRegister(CFI.getRegister(), OS, TRI); 634 break; 635 case MCCFIInstruction::OpDefCfaOffset: 636 OS << "def_cfa_offset "; 637 if (MCSymbol *Label = CFI.getLabel()) 638 MachineOperand::printSymbol(OS, *Label); 639 OS << CFI.getOffset(); 640 break; 641 case MCCFIInstruction::OpDefCfa: 642 OS << "def_cfa "; 643 if (MCSymbol *Label = CFI.getLabel()) 644 MachineOperand::printSymbol(OS, *Label); 645 printCFIRegister(CFI.getRegister(), OS, TRI); 646 OS << ", " << CFI.getOffset(); 647 break; 648 case MCCFIInstruction::OpRelOffset: 649 OS << "rel_offset "; 650 if (MCSymbol *Label = CFI.getLabel()) 651 MachineOperand::printSymbol(OS, *Label); 652 printCFIRegister(CFI.getRegister(), OS, TRI); 653 OS << ", " << CFI.getOffset(); 654 break; 655 case MCCFIInstruction::OpAdjustCfaOffset: 656 OS << "adjust_cfa_offset "; 657 if (MCSymbol *Label = CFI.getLabel()) 658 MachineOperand::printSymbol(OS, *Label); 659 OS << CFI.getOffset(); 660 break; 661 case MCCFIInstruction::OpRestore: 662 OS << "restore "; 663 if (MCSymbol *Label = CFI.getLabel()) 664 MachineOperand::printSymbol(OS, *Label); 665 printCFIRegister(CFI.getRegister(), OS, TRI); 666 break; 667 case MCCFIInstruction::OpEscape: { 668 OS << "escape "; 669 if (MCSymbol *Label = CFI.getLabel()) 670 MachineOperand::printSymbol(OS, *Label); 671 if (!CFI.getValues().empty()) { 672 size_t e = CFI.getValues().size() - 1; 673 for (size_t i = 0; i < e; ++i) 674 OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", "; 675 OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", "; 676 } 677 break; 678 } 679 case MCCFIInstruction::OpUndefined: 680 OS << "undefined "; 681 if (MCSymbol *Label = CFI.getLabel()) 682 MachineOperand::printSymbol(OS, *Label); 683 printCFIRegister(CFI.getRegister(), OS, TRI); 684 break; 685 case MCCFIInstruction::OpRegister: 686 OS << "register "; 687 if (MCSymbol *Label = CFI.getLabel()) 688 MachineOperand::printSymbol(OS, *Label); 689 printCFIRegister(CFI.getRegister(), OS, TRI); 690 OS << ", "; 691 printCFIRegister(CFI.getRegister2(), OS, TRI); 692 break; 693 case MCCFIInstruction::OpWindowSave: 694 OS << "window_save "; 695 if (MCSymbol *Label = CFI.getLabel()) 696 MachineOperand::printSymbol(OS, *Label); 697 break; 698 default: 699 // TODO: Print the other CFI Operations. 700 OS << "<unserializable cfi directive>"; 701 break; 702 } 703 } 704 705 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI, 706 const TargetIntrinsicInfo *IntrinsicInfo) const { 707 print(OS, LLT{}, TRI, IntrinsicInfo); 708 } 709 710 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint, 711 const TargetRegisterInfo *TRI, 712 const TargetIntrinsicInfo *IntrinsicInfo) const { 713 tryToGetTargetInfo(*this, TRI, IntrinsicInfo); 714 ModuleSlotTracker DummyMST(nullptr); 715 print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true, 716 /*ShouldPrintRegisterTies=*/true, 717 /*TiedOperandIdx=*/0, TRI, IntrinsicInfo); 718 } 719 720 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, 721 LLT TypeToPrint, bool PrintDef, bool IsStandalone, 722 bool ShouldPrintRegisterTies, 723 unsigned TiedOperandIdx, 724 const TargetRegisterInfo *TRI, 725 const TargetIntrinsicInfo *IntrinsicInfo) const { 726 printTargetFlags(OS, *this); 727 switch (getType()) { 728 case MachineOperand::MO_Register: { 729 unsigned Reg = getReg(); 730 if (isImplicit()) 731 OS << (isDef() ? "implicit-def " : "implicit "); 732 else if (PrintDef && isDef()) 733 // Print the 'def' flag only when the operand is defined after '='. 734 OS << "def "; 735 if (isInternalRead()) 736 OS << "internal "; 737 if (isDead()) 738 OS << "dead "; 739 if (isKill()) 740 OS << "killed "; 741 if (isUndef()) 742 OS << "undef "; 743 if (isEarlyClobber()) 744 OS << "early-clobber "; 745 if (isDebug()) 746 OS << "debug-use "; 747 if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable()) 748 OS << "renamable "; 749 750 const MachineRegisterInfo *MRI = nullptr; 751 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 752 if (const MachineFunction *MF = getMFIfAvailable(*this)) { 753 MRI = &MF->getRegInfo(); 754 } 755 } 756 757 OS << printReg(Reg, TRI, 0, MRI); 758 // Print the sub register. 759 if (unsigned SubReg = getSubReg()) { 760 if (TRI) 761 OS << '.' << TRI->getSubRegIndexName(SubReg); 762 else 763 OS << ".subreg" << SubReg; 764 } 765 // Print the register class / bank. 766 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 767 if (const MachineFunction *MF = getMFIfAvailable(*this)) { 768 const MachineRegisterInfo &MRI = MF->getRegInfo(); 769 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) { 770 OS << ':'; 771 OS << printRegClassOrBank(Reg, MRI, TRI); 772 } 773 } 774 } 775 // Print ties. 776 if (ShouldPrintRegisterTies && isTied() && !isDef()) 777 OS << "(tied-def " << TiedOperandIdx << ")"; 778 // Print types. 779 if (TypeToPrint.isValid()) 780 OS << '(' << TypeToPrint << ')'; 781 break; 782 } 783 case MachineOperand::MO_Immediate: 784 OS << getImm(); 785 break; 786 case MachineOperand::MO_CImmediate: 787 getCImm()->printAsOperand(OS, /*PrintType=*/true, MST); 788 break; 789 case MachineOperand::MO_FPImmediate: 790 getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST); 791 break; 792 case MachineOperand::MO_MachineBasicBlock: 793 OS << printMBBReference(*getMBB()); 794 break; 795 case MachineOperand::MO_FrameIndex: { 796 int FrameIndex = getIndex(); 797 bool IsFixed = false; 798 const MachineFrameInfo *MFI = nullptr; 799 if (const MachineFunction *MF = getMFIfAvailable(*this)) 800 MFI = &MF->getFrameInfo(); 801 printFrameIndex(OS, FrameIndex, IsFixed, MFI); 802 break; 803 } 804 case MachineOperand::MO_ConstantPoolIndex: 805 OS << "%const." << getIndex(); 806 printOperandOffset(OS, getOffset()); 807 break; 808 case MachineOperand::MO_TargetIndex: { 809 OS << "target-index("; 810 const char *Name = "<unknown>"; 811 if (const MachineFunction *MF = getMFIfAvailable(*this)) 812 if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex())) 813 Name = TargetIndexName; 814 OS << Name << ')'; 815 printOperandOffset(OS, getOffset()); 816 break; 817 } 818 case MachineOperand::MO_JumpTableIndex: 819 OS << printJumpTableEntryReference(getIndex()); 820 break; 821 case MachineOperand::MO_GlobalAddress: 822 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST); 823 printOperandOffset(OS, getOffset()); 824 break; 825 case MachineOperand::MO_ExternalSymbol: { 826 StringRef Name = getSymbolName(); 827 OS << '&'; 828 if (Name.empty()) { 829 OS << "\"\""; 830 } else { 831 printLLVMNameWithoutPrefix(OS, Name); 832 } 833 printOperandOffset(OS, getOffset()); 834 break; 835 } 836 case MachineOperand::MO_BlockAddress: { 837 OS << "blockaddress("; 838 getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false, 839 MST); 840 OS << ", "; 841 printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST); 842 OS << ')'; 843 MachineOperand::printOperandOffset(OS, getOffset()); 844 break; 845 } 846 case MachineOperand::MO_RegisterMask: { 847 OS << "<regmask"; 848 if (TRI) { 849 unsigned NumRegsInMask = 0; 850 unsigned NumRegsEmitted = 0; 851 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) { 852 unsigned MaskWord = i / 32; 853 unsigned MaskBit = i % 32; 854 if (getRegMask()[MaskWord] & (1 << MaskBit)) { 855 if (PrintRegMaskNumRegs < 0 || 856 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) { 857 OS << " " << printReg(i, TRI); 858 NumRegsEmitted++; 859 } 860 NumRegsInMask++; 861 } 862 } 863 if (NumRegsEmitted != NumRegsInMask) 864 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more..."; 865 } else { 866 OS << " ..."; 867 } 868 OS << ">"; 869 break; 870 } 871 case MachineOperand::MO_RegisterLiveOut: { 872 const uint32_t *RegMask = getRegLiveOut(); 873 OS << "liveout("; 874 if (!TRI) { 875 OS << "<unknown>"; 876 } else { 877 bool IsCommaNeeded = false; 878 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) { 879 if (RegMask[Reg / 32] & (1U << (Reg % 32))) { 880 if (IsCommaNeeded) 881 OS << ", "; 882 OS << printReg(Reg, TRI); 883 IsCommaNeeded = true; 884 } 885 } 886 } 887 OS << ")"; 888 break; 889 } 890 case MachineOperand::MO_Metadata: 891 getMetadata()->printAsOperand(OS, MST); 892 break; 893 case MachineOperand::MO_MCSymbol: 894 printSymbol(OS, *getMCSymbol()); 895 break; 896 case MachineOperand::MO_CFIIndex: { 897 if (const MachineFunction *MF = getMFIfAvailable(*this)) 898 printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI); 899 else 900 OS << "<cfi directive>"; 901 break; 902 } 903 case MachineOperand::MO_IntrinsicID: { 904 Intrinsic::ID ID = getIntrinsicID(); 905 if (ID < Intrinsic::num_intrinsics) 906 OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')'; 907 else if (IntrinsicInfo) 908 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')'; 909 else 910 OS << "intrinsic(" << ID << ')'; 911 break; 912 } 913 case MachineOperand::MO_Predicate: { 914 auto Pred = static_cast<CmpInst::Predicate>(getPredicate()); 915 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred(" 916 << CmpInst::getPredicateName(Pred) << ')'; 917 break; 918 } 919 } 920 } 921 922 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 923 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; } 924 #endif 925 926 //===----------------------------------------------------------------------===// 927 // MachineMemOperand Implementation 928 //===----------------------------------------------------------------------===// 929 930 /// getAddrSpace - Return the LLVM IR address space number that this pointer 931 /// points into. 932 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; } 933 934 /// isDereferenceable - Return true if V is always dereferenceable for 935 /// Offset + Size byte. 936 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C, 937 const DataLayout &DL) const { 938 if (!V.is<const Value *>()) 939 return false; 940 941 const Value *BasePtr = V.get<const Value *>(); 942 if (BasePtr == nullptr) 943 return false; 944 945 return isDereferenceableAndAlignedPointer( 946 BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL); 947 } 948 949 /// getConstantPool - Return a MachinePointerInfo record that refers to the 950 /// constant pool. 951 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) { 952 return MachinePointerInfo(MF.getPSVManager().getConstantPool()); 953 } 954 955 /// getFixedStack - Return a MachinePointerInfo record that refers to the 956 /// the specified FrameIndex. 957 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF, 958 int FI, int64_t Offset) { 959 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset); 960 } 961 962 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) { 963 return MachinePointerInfo(MF.getPSVManager().getJumpTable()); 964 } 965 966 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) { 967 return MachinePointerInfo(MF.getPSVManager().getGOT()); 968 } 969 970 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF, 971 int64_t Offset, uint8_t ID) { 972 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID); 973 } 974 975 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) { 976 return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace()); 977 } 978 979 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f, 980 uint64_t s, uint64_t a, 981 const AAMDNodes &AAInfo, 982 const MDNode *Ranges, SyncScope::ID SSID, 983 AtomicOrdering Ordering, 984 AtomicOrdering FailureOrdering) 985 : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1), 986 AAInfo(AAInfo), Ranges(Ranges) { 987 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() || 988 isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) && 989 "invalid pointer value"); 990 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 991 assert((isLoad() || isStore()) && "Not a load/store!"); 992 993 AtomicInfo.SSID = static_cast<unsigned>(SSID); 994 assert(getSyncScopeID() == SSID && "Value truncated"); 995 AtomicInfo.Ordering = static_cast<unsigned>(Ordering); 996 assert(getOrdering() == Ordering && "Value truncated"); 997 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering); 998 assert(getFailureOrdering() == FailureOrdering && "Value truncated"); 999 } 1000 1001 /// Profile - Gather unique data for the object. 1002 /// 1003 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 1004 ID.AddInteger(getOffset()); 1005 ID.AddInteger(Size); 1006 ID.AddPointer(getOpaqueValue()); 1007 ID.AddInteger(getFlags()); 1008 ID.AddInteger(getBaseAlignment()); 1009 } 1010 1011 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 1012 // The Value and Offset may differ due to CSE. But the flags and size 1013 // should be the same. 1014 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 1015 assert(MMO->getSize() == getSize() && "Size mismatch!"); 1016 1017 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 1018 // Update the alignment value. 1019 BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1; 1020 // Also update the base and offset, because the new alignment may 1021 // not be applicable with the old ones. 1022 PtrInfo = MMO->PtrInfo; 1023 } 1024 } 1025 1026 /// getAlignment - Return the minimum known alignment in bytes of the 1027 /// actual memory reference. 1028 uint64_t MachineMemOperand::getAlignment() const { 1029 return MinAlign(getBaseAlignment(), getOffset()); 1030 } 1031 1032 void MachineMemOperand::print(raw_ostream &OS) const { 1033 ModuleSlotTracker DummyMST(nullptr); 1034 print(OS, DummyMST); 1035 } 1036 1037 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const { 1038 SmallVector<StringRef, 0> SSNs; 1039 LLVMContext Ctx; 1040 print(OS, MST, SSNs, Ctx, nullptr, nullptr); 1041 } 1042 1043 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, 1044 SmallVectorImpl<StringRef> &SSNs, 1045 const LLVMContext &Context, 1046 const MachineFrameInfo *MFI, 1047 const TargetInstrInfo *TII) const { 1048 OS << '('; 1049 if (isVolatile()) 1050 OS << "volatile "; 1051 if (isNonTemporal()) 1052 OS << "non-temporal "; 1053 if (isDereferenceable()) 1054 OS << "dereferenceable "; 1055 if (isInvariant()) 1056 OS << "invariant "; 1057 if (getFlags() & MachineMemOperand::MOTargetFlag1) 1058 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1) 1059 << "\" "; 1060 if (getFlags() & MachineMemOperand::MOTargetFlag2) 1061 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2) 1062 << "\" "; 1063 if (getFlags() & MachineMemOperand::MOTargetFlag3) 1064 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3) 1065 << "\" "; 1066 1067 assert((isLoad() || isStore()) && 1068 "machine memory operand must be a load or store (or both)"); 1069 if (isLoad()) 1070 OS << "load "; 1071 if (isStore()) 1072 OS << "store "; 1073 1074 printSyncScope(OS, Context, getSyncScopeID(), SSNs); 1075 1076 if (getOrdering() != AtomicOrdering::NotAtomic) 1077 OS << toIRString(getOrdering()) << ' '; 1078 if (getFailureOrdering() != AtomicOrdering::NotAtomic) 1079 OS << toIRString(getFailureOrdering()) << ' '; 1080 1081 OS << getSize(); 1082 if (const Value *Val = getValue()) { 1083 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into "); 1084 printIRValueReference(OS, *Val, MST); 1085 } else if (const PseudoSourceValue *PVal = getPseudoValue()) { 1086 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into "); 1087 assert(PVal && "Expected a pseudo source value"); 1088 switch (PVal->kind()) { 1089 case PseudoSourceValue::Stack: 1090 OS << "stack"; 1091 break; 1092 case PseudoSourceValue::GOT: 1093 OS << "got"; 1094 break; 1095 case PseudoSourceValue::JumpTable: 1096 OS << "jump-table"; 1097 break; 1098 case PseudoSourceValue::ConstantPool: 1099 OS << "constant-pool"; 1100 break; 1101 case PseudoSourceValue::FixedStack: { 1102 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex(); 1103 bool IsFixed = true; 1104 printFrameIndex(OS, FrameIndex, IsFixed, MFI); 1105 break; 1106 } 1107 case PseudoSourceValue::GlobalValueCallEntry: 1108 OS << "call-entry "; 1109 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand( 1110 OS, /*PrintType=*/false, MST); 1111 break; 1112 case PseudoSourceValue::ExternalSymbolCallEntry: 1113 OS << "call-entry &"; 1114 printLLVMNameWithoutPrefix( 1115 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol()); 1116 break; 1117 case PseudoSourceValue::TargetCustom: 1118 // FIXME: This is not necessarily the correct MIR serialization format for 1119 // a custom pseudo source value, but at least it allows 1120 // -print-machineinstrs to work on a target with custom pseudo source 1121 // values. 1122 OS << "custom "; 1123 PVal->printCustom(OS); 1124 break; 1125 } 1126 } 1127 MachineOperand::printOperandOffset(OS, getOffset()); 1128 if (getBaseAlignment() != getSize()) 1129 OS << ", align " << getBaseAlignment(); 1130 auto AAInfo = getAAInfo(); 1131 if (AAInfo.TBAA) { 1132 OS << ", !tbaa "; 1133 AAInfo.TBAA->printAsOperand(OS, MST); 1134 } 1135 if (AAInfo.Scope) { 1136 OS << ", !alias.scope "; 1137 AAInfo.Scope->printAsOperand(OS, MST); 1138 } 1139 if (AAInfo.NoAlias) { 1140 OS << ", !noalias "; 1141 AAInfo.NoAlias->printAsOperand(OS, MST); 1142 } 1143 if (getRanges()) { 1144 OS << ", !range "; 1145 getRanges()->printAsOperand(OS, MST); 1146 } 1147 // FIXME: Implement addrspace printing/parsing in MIR. 1148 // For now, print this even though parsing it is not available in MIR. 1149 if (unsigned AS = getAddrSpace()) 1150 OS << ", addrspace " << AS; 1151 1152 OS << ')'; 1153 } 1154