1 /************************************************************************** 2 * 3 * Copyright 2017 Advanced Micro Devices, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #ifndef _RADEON_VCN_ENC_H 29 #define _RADEON_VCN_ENC_H 30 31 #define RENCODE_FW_INTERFACE_MAJOR_VERSION 1 32 #define RENCODE_FW_INTERFACE_MINOR_VERSION 2 33 34 #define RENCODE_IB_PARAM_SESSION_INFO 0x00000001 35 #define RENCODE_IB_PARAM_TASK_INFO 0x00000002 36 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 37 #define RENCODE_IB_PARAM_LAYER_CONTROL 0x00000004 38 #define RENCODE_IB_PARAM_LAYER_SELECT 0x00000005 39 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006 40 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT 0x00000007 41 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE 0x00000008 42 #define RENCODE_IB_PARAM_QUALITY_PARAMS 0x00000009 43 #define RENCODE_IB_PARAM_SLICE_HEADER 0x0000000a 44 #define RENCODE_IB_PARAM_ENCODE_PARAMS 0x0000000b 45 #define RENCODE_IB_PARAM_INTRA_REFRESH 0x0000000c 46 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x0000000d 47 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e 48 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010 49 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020 50 51 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001 52 #define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002 53 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003 54 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004 55 56 #define RENCODE_IB_OP_INITIALIZE 0x01000001 57 #define RENCODE_IB_OP_CLOSE_SESSION 0x01000002 58 #define RENCODE_IB_OP_ENCODE 0x01000003 59 #define RENCODE_IB_OP_INIT_RC 0x01000004 60 #define RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL 0x01000005 61 #define RENCODE_IB_OP_SET_SPEED_ENCODING_MODE 0x01000006 62 #define RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE 0x01000007 63 #define RENCODE_IB_OP_SET_QUALITY_ENCODING_MODE 0x01000008 64 65 #define RENCODE_IF_MAJOR_VERSION_MASK 0xFFFF0000 66 #define RENCODE_IF_MAJOR_VERSION_SHIFT 16 67 #define RENCODE_IF_MINOR_VERSION_MASK 0x0000FFFF 68 #define RENCODE_IF_MINOR_VERSION_SHIFT 0 69 70 #define RENCODE_ENCODE_STANDARD_H264 1 71 72 #define RENCODE_PREENCODE_MODE_NONE 0x00000000 73 #define RENCODE_PREENCODE_MODE_1X 0x00000001 74 #define RENCODE_PREENCODE_MODE_2X 0x00000002 75 #define RENCODE_PREENCODE_MODE_4X 0x00000004 76 77 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS 0x00000000 78 #define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001 79 80 #define RENCODE_RATE_CONTROL_METHOD_NONE 0x00000000 81 #define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001 82 #define RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR 0x00000002 83 #define RENCODE_RATE_CONTROL_METHOD_CBR 0x00000003 84 85 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD 0x00000000 86 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS 0x00000001 87 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS 0x00000002 88 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS 0x00000003 89 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_PREFIX 0x00000004 90 #define RENCODE_DIRECT_OUTPUT_NALU_TYPE_END_OF_SEQUENCE 0x00000005 91 92 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS 16 93 #define RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS 16 94 95 #define RENCODE_HEADER_INSTRUCTION_END 0x00000000 96 #define RENCODE_HEADER_INSTRUCTION_COPY 0x00000001 97 98 #define RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB 0x00020000 99 #define RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA 0x00020001 100 101 #define RENCODE_PICTURE_TYPE_B 0 102 #define RENCODE_PICTURE_TYPE_P 1 103 #define RENCODE_PICTURE_TYPE_I 2 104 #define RENCODE_PICTURE_TYPE_P_SKIP 3 105 106 #define RENCODE_INPUT_SWIZZLE_MODE_LINEAR 0 107 #define RENCODE_INPUT_SWIZZLE_MODE_256B_S 1 108 #define RENCODE_INPUT_SWIZZLE_MODE_4kB_S 5 109 #define RENCODE_INPUT_SWIZZLE_MODE_64kB_S 9 110 111 #define RENCODE_H264_PICTURE_STRUCTURE_FRAME 0 112 #define RENCODE_H264_PICTURE_STRUCTURE_TOP_FIELD 1 113 #define RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD 2 114 115 #define RENCODE_H264_INTERLACING_MODE_PROGRESSIVE 0 116 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_STACKED 1 117 #define RENCODE_H264_INTERLACING_MODE_INTERLACED_INTERLEAVED 2 118 119 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE 0 120 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 1 121 #define RENCODE_H264_DISABLE_DEBLOCKING_FILTER_IDC_DISALBE_ACROSS_SLICE_BOUNDARY 2 122 123 #define RENCODE_INTRA_REFRESH_MODE_NONE 0 124 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_ROWS 1 125 #define RENCODE_INTRA_REFRESH_MODE_CTB_MB_COLUMNS 2 126 127 #define RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES 34 128 129 #define RENCODE_REC_SWIZZLE_MODE_LINEAR 0 130 #define RENCODE_REC_SWIZZLE_MODE_256B_S 1 131 132 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_LINEAR 0 133 #define RENCODE_VIDEO_BITSTREAM_BUFFER_MODE_CIRCULAR 1 134 135 #define RENCODE_FEEDBACK_BUFFER_MODE_LINEAR 0 136 #define RENCODE_FEEDBACK_BUFFER_MODE_CIRCULAR 1 137 138 typedef struct rvcn_enc_session_info_s 139 { 140 uint32_t interface_version; 141 uint32_t sw_context_address_hi; 142 uint32_t sw_context_address_lo; 143 } rvcn_enc_session_info_t; 144 145 typedef struct rvcn_enc_task_info_s 146 { 147 uint32_t total_size_of_all_packages; 148 uint32_t task_id; 149 uint32_t allowed_max_num_feedbacks; 150 } rvcn_enc_task_info_t; 151 152 typedef struct rvcn_enc_session_init_s 153 { 154 uint32_t encode_standard; 155 uint32_t aligned_picture_width; 156 uint32_t aligned_picture_height; 157 uint32_t padding_width; 158 uint32_t padding_height; 159 uint32_t pre_encode_mode; 160 uint32_t pre_encode_chroma_enabled; 161 } rvcn_enc_session_init_t; 162 163 typedef struct rvcn_enc_layer_control_s 164 { 165 uint32_t max_num_temporal_layers; 166 uint32_t num_temporal_layers; 167 } rvcn_enc_layer_control_t; 168 169 typedef struct rvcn_enc_layer_select_s 170 { 171 uint32_t temporal_layer_index; 172 } rvcn_enc_layer_select_t; 173 174 typedef struct rvcn_enc_h264_slice_control_s 175 { 176 uint32_t slice_control_mode; 177 union 178 { 179 uint32_t num_mbs_per_slice; 180 uint32_t num_bits_per_slice; 181 }; 182 } rvcn_enc_h264_slice_control_t; 183 184 typedef struct rvcn_enc_h264_spec_misc_s 185 { 186 uint32_t constrained_intra_pred_flag; 187 uint32_t cabac_enable; 188 uint32_t cabac_init_idc; 189 uint32_t half_pel_enabled; 190 uint32_t quarter_pel_enabled; 191 uint32_t profile_idc; 192 uint32_t level_idc; 193 } rvcn_enc_h264_spec_misc_t; 194 195 typedef struct rvcn_enc_rate_ctl_session_init_s 196 { 197 uint32_t rate_control_method; 198 uint32_t vbv_buffer_level; 199 } rvcn_enc_rate_ctl_session_init_t; 200 201 typedef struct rvcn_enc_rate_ctl_layer_init_s 202 { 203 uint32_t target_bit_rate; 204 uint32_t peak_bit_rate; 205 uint32_t frame_rate_num; 206 uint32_t frame_rate_den; 207 uint32_t vbv_buffer_size; 208 uint32_t avg_target_bits_per_picture; 209 uint32_t peak_bits_per_picture_integer; 210 uint32_t peak_bits_per_picture_fractional; 211 } rvcn_enc_rate_ctl_layer_init_t; 212 213 typedef struct rvcn_enc_rate_ctl_per_picture_s 214 { 215 uint32_t qp; 216 uint32_t min_qp_app; 217 uint32_t max_qp_app; 218 uint32_t max_au_size; 219 uint32_t enabled_filler_data; 220 uint32_t skip_frame_enable; 221 uint32_t enforce_hrd; 222 } rvcn_enc_rate_ctl_per_picture_t; 223 224 typedef struct rvcn_enc_quality_params_s 225 { 226 uint32_t vbaq_mode; 227 uint32_t scene_change_sensitivity; 228 uint32_t scene_change_min_idr_interval; 229 } rvcn_enc_quality_params_t; 230 231 typedef struct rvcn_enc_direct_output_nalu_s 232 { 233 uint32_t type; 234 uint32_t size; 235 uint32_t data[1]; 236 } rvcn_enc_direct_output_nalu_t; 237 238 typedef struct rvcn_enc_slice_header_s 239 { 240 uint32_t bitstream_template[RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS]; 241 struct { 242 uint32_t instruction; 243 uint32_t num_bits; 244 } instructions[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS]; 245 } rvcn_enc_slice_header_t; 246 247 typedef struct rvcn_enc_encode_params_s 248 { 249 uint32_t pic_type; 250 uint32_t allowed_max_bitstream_size; 251 uint32_t input_picture_luma_address_hi; 252 uint32_t input_picture_luma_address_lo; 253 uint32_t input_picture_chroma_address_hi; 254 uint32_t input_picture_chroma_address_lo; 255 uint32_t input_pic_luma_pitch; 256 uint32_t input_pic_chroma_pitch; 257 uint8_t input_pic_swizzle_mode; 258 uint32_t reference_picture_index; 259 uint32_t reconstructed_picture_index; 260 } rvcn_enc_encode_params_t; 261 262 typedef struct rvcn_enc_h264_encode_params_s 263 { 264 uint32_t input_picture_structure; 265 uint32_t interlaced_mode; 266 uint32_t reference_picture_structure; 267 uint32_t reference_picture1_index; 268 } rvcn_enc_h264_encode_params_t; 269 270 typedef struct rvcn_enc_h264_deblocking_filter_s 271 { 272 uint32_t disable_deblocking_filter_idc; 273 int32_t alpha_c0_offset_div2; 274 int32_t beta_offset_div2; 275 int32_t cb_qp_offset; 276 int32_t cr_qp_offset; 277 } rvcn_enc_h264_deblocking_filter_t; 278 279 typedef struct rvcn_enc_intra_refresh_s 280 { 281 uint32_t intra_refresh_mode; 282 uint32_t offset; 283 uint32_t region_size; 284 } rvcn_enc_intra_refresh_t; 285 286 typedef struct rvcn_enc_reconstructed_picture_s 287 { 288 uint32_t luma_offset; 289 uint32_t chroma_offset; 290 } rvcn_enc_reconstructed_picture_t; 291 292 typedef struct rvcn_enc_encode_context_buffer_s 293 { 294 uint32_t encode_context_address_hi; 295 uint32_t encode_context_address_lo; 296 uint32_t swizzle_mode; 297 uint32_t rec_luma_pitch; 298 uint32_t rec_chroma_pitch; 299 uint32_t num_reconstructed_pictures; 300 rvcn_enc_reconstructed_picture_t reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 301 uint32_t pre_encode_picture_luma_pitch; 302 uint32_t pre_encode_picture_chroma_pitch; 303 rvcn_enc_reconstructed_picture_t pre_encode_reconstructed_pictures[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES]; 304 rvcn_enc_reconstructed_picture_t pre_encode_input_picture; 305 } rvcn_enc_encode_context_buffer_t; 306 307 typedef struct rvcn_enc_video_bitstream_buffer_s 308 { 309 uint32_t mode; 310 uint32_t video_bitstream_buffer_address_hi; 311 uint32_t video_bitstream_buffer_address_lo; 312 uint32_t video_bitstream_buffer_size; 313 uint32_t video_bitstream_data_offset; 314 } rvcn_enc_video_bitstream_buffer_t; 315 316 typedef struct rvcn_enc_feedback_buffer_s 317 { 318 uint32_t mode; 319 uint32_t feedback_buffer_address_hi; 320 uint32_t feedback_buffer_address_lo; 321 uint32_t feedback_buffer_size; 322 uint32_t feedback_data_size; 323 } rvcn_enc_feedback_buffer_t; 324 325 typedef void (*radeon_enc_get_buffer)(struct pipe_resource *resource, 326 struct pb_buffer **handle, 327 struct radeon_surf **surface); 328 329 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context, 330 const struct pipe_video_codec *templat, 331 struct radeon_winsys* ws, 332 radeon_enc_get_buffer get_buffer); 333 334 struct radeon_enc_h264_enc_pic { 335 enum pipe_h264_enc_picture_type picture_type; 336 337 unsigned frame_num; 338 unsigned pic_order_cnt; 339 unsigned pic_order_cnt_type; 340 unsigned ref_idx_l0; 341 unsigned ref_idx_l1; 342 unsigned crop_left; 343 unsigned crop_right; 344 unsigned crop_top; 345 unsigned crop_bottom; 346 347 bool not_referenced; 348 bool is_idr; 349 bool is_even_frame; 350 351 rvcn_enc_task_info_t task_info; 352 rvcn_enc_session_init_t session_init; 353 rvcn_enc_layer_control_t layer_ctrl; 354 rvcn_enc_layer_select_t layer_sel; 355 rvcn_enc_h264_slice_control_t slice_ctrl; 356 rvcn_enc_h264_spec_misc_t spec_misc; 357 rvcn_enc_rate_ctl_session_init_t rc_session_init; 358 rvcn_enc_rate_ctl_layer_init_t rc_layer_init; 359 rvcn_enc_h264_encode_params_t h264_enc_params; 360 rvcn_enc_h264_deblocking_filter_t h264_deblock; 361 rvcn_enc_rate_ctl_per_picture_t rc_per_pic; 362 rvcn_enc_quality_params_t quality_params; 363 rvcn_enc_encode_context_buffer_t ctx_buf; 364 rvcn_enc_video_bitstream_buffer_t bit_buf; 365 rvcn_enc_feedback_buffer_t fb_buf; 366 rvcn_enc_intra_refresh_t intra_ref; 367 rvcn_enc_encode_params_t enc_params; 368 }; 369 370 struct radeon_encoder { 371 struct pipe_video_codec base; 372 373 void (*begin)(struct radeon_encoder *enc, struct pipe_h264_enc_picture_desc *pic); 374 void (*encode)(struct radeon_encoder *enc); 375 void (*destroy)(struct radeon_encoder *enc); 376 377 unsigned stream_handle; 378 379 struct pipe_screen *screen; 380 struct radeon_winsys* ws; 381 struct radeon_winsys_cs* cs; 382 383 radeon_enc_get_buffer get_buffer; 384 385 struct pb_buffer* handle; 386 struct radeon_surf* luma; 387 struct radeon_surf* chroma; 388 389 struct pb_buffer* bs_handle; 390 unsigned bs_size; 391 392 unsigned cpb_num; 393 394 struct rvid_buffer *si; 395 struct rvid_buffer *fb; 396 struct rvid_buffer cpb; 397 struct radeon_enc_h264_enc_pic enc_pic; 398 399 unsigned alignment; 400 unsigned shifter; 401 unsigned bits_in_shifter; 402 unsigned num_zeros; 403 unsigned byte_index; 404 unsigned bits_output; 405 uint32_t total_task_size; 406 uint32_t* p_task_size; 407 408 bool emulation_prevention; 409 bool need_feedback; 410 }; 411 412 void radeon_enc_1_2_init(struct radeon_encoder *enc); 413 414 #endif // _RADEON_VCN_ENC_H 415
