1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2003 4 * Thomas.Lange (at) corelatus.se 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <mach/au1x00.h> 10 #include <asm/mipsregs.h> 11 #include <asm/io.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 int dram_init(void) 16 { 17 /* Sdram is setup by assembler code */ 18 /* If memory could be changed, we should return the true value here */ 19 gd->ram_size = MEM_SIZE * 1024 * 1024; 20 21 return 0; 22 } 23 24 #define BCSR_PCMCIA_PC0DRVEN 0x0010 25 #define BCSR_PCMCIA_PC0RST 0x0080 26 27 /* In arch/mips/cpu/cpu.c */ 28 void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ); 29 30 int checkboard (void) 31 { 32 #ifdef CONFIG_IDE_PCMCIA 33 u16 status; 34 volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10); 35 #endif /* CONFIG_IDE_PCMCIA */ 36 volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC); 37 volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL; 38 u32 proc_id; 39 40 *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */ 41 42 proc_id = read_c0_prid(); 43 44 switch (proc_id >> 24) { 45 case 0: 46 puts ("Board: Merlot (DbAu1000)\n"); 47 printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n", 48 (proc_id >> 8) & 0xFF, proc_id & 0xFF); 49 break; 50 case 1: 51 puts ("Board: DbAu1500\n"); 52 printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n", 53 (proc_id >> 8) & 0xFF, proc_id & 0xFF); 54 break; 55 case 2: 56 puts ("Board: DbAu1100\n"); 57 printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n", 58 (proc_id >> 8) & 0xFF, proc_id & 0xFF); 59 break; 60 case 3: 61 puts ("Board: DbAu1550\n"); 62 printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n", 63 (proc_id >> 8) & 0xFF, proc_id & 0xFF); 64 break; 65 default: 66 printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); 67 } 68 69 set_io_port_base(0); 70 71 #ifdef CONFIG_IDE_PCMCIA 72 /* Enable 3.3 V on slot 0 ( VCC ) 73 No 5V */ 74 status = 4; 75 *pcmcia_bcsr = status; 76 77 status |= BCSR_PCMCIA_PC0DRVEN; 78 *pcmcia_bcsr = status; 79 au_sync(); 80 81 udelay(300*1000); 82 83 status |= BCSR_PCMCIA_PC0RST; 84 *pcmcia_bcsr = status; 85 au_sync(); 86 87 udelay(100*1000); 88 89 /* PCMCIA is on a 36 bit physical address. 90 We need to map it into a 32 bit addresses */ 91 92 #if 0 93 /* We dont need theese unless we run whole pcmcia package */ 94 write_one_tlb(20, /* index */ 95 0x01ffe000, /* Pagemask, 16 MB pages */ 96 CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */ 97 0x3C000017, /* Lo0 */ 98 0x3C200017); /* Lo1 */ 99 100 write_one_tlb(21, /* index */ 101 0x01ffe000, /* Pagemask, 16 MB pages */ 102 CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */ 103 0x3D000017, /* Lo0 */ 104 0x3D200017); /* Lo1 */ 105 #endif /* 0 */ 106 write_one_tlb(22, /* index */ 107 0x01ffe000, /* Pagemask, 16 MB pages */ 108 CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */ 109 0x3E000017, /* Lo0 */ 110 0x3E200017); /* Lo1 */ 111 #endif /* CONFIG_IDE_PCMCIA */ 112 113 /* Release reset of ethernet PHY chips */ 114 /* Always do this, because linux does not know about it */ 115 *phy = 3; 116 117 return 0; 118 } 119
