1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2011 Freescale Semiconductor 4 * Author: Shengzhou Liu <Shengzhou.Liu (at) freescale.com> 5 * 6 * This file provides support for the QIXIS of some Freescale reference boards. 7 */ 8 9 #include <common.h> 10 #include <command.h> 11 #include <asm/io.h> 12 #include <linux/compiler.h> 13 #include <linux/time.h> 14 #include <i2c.h> 15 #include "qixis.h" 16 17 #ifndef QIXIS_LBMAP_BRDCFG_REG 18 /* 19 * For consistency with existing platforms 20 */ 21 #define QIXIS_LBMAP_BRDCFG_REG 0x00 22 #endif 23 24 #ifdef CONFIG_SYS_I2C_FPGA_ADDR 25 u8 qixis_read_i2c(unsigned int reg) 26 { 27 return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); 28 } 29 30 void qixis_write_i2c(unsigned int reg, u8 value) 31 { 32 u8 val = value; 33 i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); 34 } 35 #endif 36 37 #ifdef QIXIS_BASE 38 u8 qixis_read(unsigned int reg) 39 { 40 void *p = (void *)QIXIS_BASE; 41 42 return in_8(p + reg); 43 } 44 45 void qixis_write(unsigned int reg, u8 value) 46 { 47 void *p = (void *)QIXIS_BASE; 48 49 out_8(p + reg, value); 50 } 51 #endif 52 53 u16 qixis_read_minor(void) 54 { 55 u16 minor; 56 57 /* this data is in little endian */ 58 QIXIS_WRITE(tagdata, 5); 59 minor = QIXIS_READ(tagdata); 60 QIXIS_WRITE(tagdata, 6); 61 minor += QIXIS_READ(tagdata) << 8; 62 63 return minor; 64 } 65 66 char *qixis_read_time(char *result) 67 { 68 time_t time = 0; 69 int i; 70 71 /* timestamp is in 32-bit big endian */ 72 for (i = 8; i <= 11; i++) { 73 QIXIS_WRITE(tagdata, i); 74 time = (time << 8) + QIXIS_READ(tagdata); 75 } 76 77 return ctime_r(&time, result); 78 } 79 80 char *qixis_read_tag(char *buf) 81 { 82 int i; 83 char tag, *ptr = buf; 84 85 for (i = 16; i <= 63; i++) { 86 QIXIS_WRITE(tagdata, i); 87 tag = QIXIS_READ(tagdata); 88 *(ptr++) = tag; 89 if (!tag) 90 break; 91 } 92 if (i > 63) 93 *ptr = '\0'; 94 95 return buf; 96 } 97 98 /* 99 * return the string of binary of u8 in the format of 100 * 1010 10_0. The masked bit is filled as underscore. 101 */ 102 const char *byte_to_binary_mask(u8 val, u8 mask, char *buf) 103 { 104 char *ptr; 105 int i; 106 107 ptr = buf; 108 for (i = 0x80; i > 0x08 ; i >>= 1, ptr++) 109 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); 110 *(ptr++) = ' '; 111 for (i = 0x08; i > 0 ; i >>= 1, ptr++) 112 *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0'); 113 114 *ptr = '\0'; 115 116 return buf; 117 } 118 119 #ifdef QIXIS_RST_FORCE_MEM 120 void board_assert_mem_reset(void) 121 { 122 u8 rst; 123 124 rst = QIXIS_READ(rst_frc[0]); 125 if (!(rst & QIXIS_RST_FORCE_MEM)) 126 QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM); 127 } 128 129 void board_deassert_mem_reset(void) 130 { 131 u8 rst; 132 133 rst = QIXIS_READ(rst_frc[0]); 134 if (rst & QIXIS_RST_FORCE_MEM) 135 QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM); 136 } 137 #endif 138 139 #ifndef CONFIG_SPL_BUILD 140 static void qixis_reset(void) 141 { 142 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); 143 } 144 145 static void qixis_bank_reset(void) 146 { 147 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE); 148 QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START); 149 } 150 151 static void __maybe_unused set_lbmap(int lbmap) 152 { 153 u8 reg; 154 155 reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); 156 reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap; 157 QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg); 158 } 159 160 static void __maybe_unused set_rcw_src(int rcw_src) 161 { 162 u8 reg; 163 164 reg = QIXIS_READ(dutcfg[1]); 165 reg = (reg & ~1) | (rcw_src & 1); 166 QIXIS_WRITE(dutcfg[1], reg); 167 QIXIS_WRITE(dutcfg[0], (rcw_src >> 1) & 0xff); 168 } 169 170 static void qixis_dump_regs(void) 171 { 172 int i; 173 174 printf("id = %02x\n", QIXIS_READ(id)); 175 printf("arch = %02x\n", QIXIS_READ(arch)); 176 printf("scver = %02x\n", QIXIS_READ(scver)); 177 printf("model = %02x\n", QIXIS_READ(model)); 178 printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl)); 179 printf("aux = %02x\n", QIXIS_READ(aux)); 180 for (i = 0; i < 16; i++) 181 printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i])); 182 for (i = 0; i < 16; i++) 183 printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i])); 184 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), 185 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); 186 printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]), 187 QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2])); 188 printf("aux = %02x\n", QIXIS_READ(aux)); 189 printf("watch = %02x\n", QIXIS_READ(watch)); 190 printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); 191 printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); 192 printf("present = %02x\n", QIXIS_READ(present)); 193 printf("present2 = %02x\n", QIXIS_READ(present2)); 194 printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); 195 printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); 196 printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); 197 printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); 198 } 199 200 void __weak qixis_dump_switch(void) 201 { 202 puts("Reverse engineering switch is not implemented for this board\n"); 203 } 204 205 static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 206 { 207 int i; 208 209 if (argc <= 1) { 210 set_lbmap(QIXIS_LBMAP_DFLTBANK); 211 qixis_reset(); 212 } else if (strcmp(argv[1], "altbank") == 0) { 213 set_lbmap(QIXIS_LBMAP_ALTBANK); 214 qixis_bank_reset(); 215 } else if (strcmp(argv[1], "nand") == 0) { 216 #ifdef QIXIS_LBMAP_NAND 217 QIXIS_WRITE(rst_ctl, 0x30); 218 QIXIS_WRITE(rcfg_ctl, 0); 219 set_lbmap(QIXIS_LBMAP_NAND); 220 set_rcw_src(QIXIS_RCW_SRC_NAND); 221 QIXIS_WRITE(rcfg_ctl, 0x20); 222 QIXIS_WRITE(rcfg_ctl, 0x21); 223 #else 224 printf("Not implemented\n"); 225 #endif 226 } else if (strcmp(argv[1], "sd") == 0) { 227 #ifdef QIXIS_LBMAP_SD 228 QIXIS_WRITE(rst_ctl, 0x30); 229 QIXIS_WRITE(rcfg_ctl, 0); 230 set_lbmap(QIXIS_LBMAP_SD); 231 set_rcw_src(QIXIS_RCW_SRC_SD); 232 QIXIS_WRITE(rcfg_ctl, 0x20); 233 QIXIS_WRITE(rcfg_ctl, 0x21); 234 #else 235 printf("Not implemented\n"); 236 #endif 237 } else if (strcmp(argv[1], "ifc") == 0) { 238 #ifdef QIXIS_LBMAP_IFC 239 QIXIS_WRITE(rst_ctl, 0x30); 240 QIXIS_WRITE(rcfg_ctl, 0); 241 set_lbmap(QIXIS_LBMAP_IFC); 242 set_rcw_src(QIXIS_RCW_SRC_IFC); 243 QIXIS_WRITE(rcfg_ctl, 0x20); 244 QIXIS_WRITE(rcfg_ctl, 0x21); 245 #else 246 printf("Not implemented\n"); 247 #endif 248 } else if (strcmp(argv[1], "emmc") == 0) { 249 #ifdef QIXIS_LBMAP_EMMC 250 QIXIS_WRITE(rst_ctl, 0x30); 251 QIXIS_WRITE(rcfg_ctl, 0); 252 set_lbmap(QIXIS_LBMAP_EMMC); 253 set_rcw_src(QIXIS_RCW_SRC_EMMC); 254 QIXIS_WRITE(rcfg_ctl, 0x20); 255 QIXIS_WRITE(rcfg_ctl, 0x21); 256 #else 257 printf("Not implemented\n"); 258 #endif 259 } else if (strcmp(argv[1], "sd_qspi") == 0) { 260 #ifdef QIXIS_LBMAP_SD_QSPI 261 QIXIS_WRITE(rst_ctl, 0x30); 262 QIXIS_WRITE(rcfg_ctl, 0); 263 set_lbmap(QIXIS_LBMAP_SD_QSPI); 264 set_rcw_src(QIXIS_RCW_SRC_SD); 265 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); 266 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); 267 #else 268 printf("Not implemented\n"); 269 #endif 270 } else if (strcmp(argv[1], "qspi") == 0) { 271 #ifdef QIXIS_LBMAP_QSPI 272 QIXIS_WRITE(rst_ctl, 0x30); 273 QIXIS_WRITE(rcfg_ctl, 0); 274 set_lbmap(QIXIS_LBMAP_QSPI); 275 set_rcw_src(QIXIS_RCW_SRC_QSPI); 276 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x20); 277 qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), 0x21); 278 #else 279 printf("Not implemented\n"); 280 #endif 281 } else if (strcmp(argv[1], "watchdog") == 0) { 282 static char *period[9] = {"2s", "4s", "8s", "16s", "32s", 283 "1min", "2min", "4min", "8min"}; 284 u8 rcfg = QIXIS_READ(rcfg_ctl); 285 286 if (argv[2] == NULL) { 287 printf("qixis watchdog <watchdog_period>\n"); 288 return 0; 289 } 290 for (i = 0; i < ARRAY_SIZE(period); i++) { 291 if (strcmp(argv[2], period[i]) == 0) { 292 /* disable watchdog */ 293 QIXIS_WRITE(rcfg_ctl, 294 rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE); 295 QIXIS_WRITE(watch, ((i<<2) - 1)); 296 QIXIS_WRITE(rcfg_ctl, rcfg); 297 return 0; 298 } 299 } 300 } else if (strcmp(argv[1], "dump") == 0) { 301 qixis_dump_regs(); 302 return 0; 303 } else if (strcmp(argv[1], "switch") == 0) { 304 qixis_dump_switch(); 305 return 0; 306 } else { 307 printf("Invalid option: %s\n", argv[1]); 308 return 1; 309 } 310 311 return 0; 312 } 313 314 U_BOOT_CMD( 315 qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd, 316 "Reset the board using the FPGA sequencer", 317 "- hard reset to default bank\n" 318 "qixis_reset altbank - reset to alternate bank\n" 319 "qixis_reset nand - reset to nand\n" 320 "qixis_reset sd - reset to sd\n" 321 "qixis_reset sd_qspi - reset to sd with qspi support\n" 322 "qixis_reset qspi - reset to qspi\n" 323 "qixis watchdog <watchdog_period> - set the watchdog period\n" 324 " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" 325 "qixis_reset dump - display the QIXIS registers\n" 326 "qixis_reset switch - display switch\n" 327 ); 328 #endif 329
