1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Designware master SPI core controller driver 4 * 5 * Copyright (C) 2014 Stefan Roese <sr (at) denx.de> 6 * 7 * Very loosely based on the Linux driver: 8 * drivers/spi/spi-dw.c, which is: 9 * Copyright (c) 2009, Intel Corporation. 10 */ 11 12 #include <asm-generic/gpio.h> 13 #include <common.h> 14 #include <clk.h> 15 #include <dm.h> 16 #include <errno.h> 17 #include <malloc.h> 18 #include <spi.h> 19 #include <fdtdec.h> 20 #include <linux/compat.h> 21 #include <linux/iopoll.h> 22 #include <asm/io.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* Register offsets */ 27 #define DW_SPI_CTRL0 0x00 28 #define DW_SPI_CTRL1 0x04 29 #define DW_SPI_SSIENR 0x08 30 #define DW_SPI_MWCR 0x0c 31 #define DW_SPI_SER 0x10 32 #define DW_SPI_BAUDR 0x14 33 #define DW_SPI_TXFLTR 0x18 34 #define DW_SPI_RXFLTR 0x1c 35 #define DW_SPI_TXFLR 0x20 36 #define DW_SPI_RXFLR 0x24 37 #define DW_SPI_SR 0x28 38 #define DW_SPI_IMR 0x2c 39 #define DW_SPI_ISR 0x30 40 #define DW_SPI_RISR 0x34 41 #define DW_SPI_TXOICR 0x38 42 #define DW_SPI_RXOICR 0x3c 43 #define DW_SPI_RXUICR 0x40 44 #define DW_SPI_MSTICR 0x44 45 #define DW_SPI_ICR 0x48 46 #define DW_SPI_DMACR 0x4c 47 #define DW_SPI_DMATDLR 0x50 48 #define DW_SPI_DMARDLR 0x54 49 #define DW_SPI_IDR 0x58 50 #define DW_SPI_VERSION 0x5c 51 #define DW_SPI_DR 0x60 52 53 /* Bit fields in CTRLR0 */ 54 #define SPI_DFS_OFFSET 0 55 56 #define SPI_FRF_OFFSET 4 57 #define SPI_FRF_SPI 0x0 58 #define SPI_FRF_SSP 0x1 59 #define SPI_FRF_MICROWIRE 0x2 60 #define SPI_FRF_RESV 0x3 61 62 #define SPI_MODE_OFFSET 6 63 #define SPI_SCPH_OFFSET 6 64 #define SPI_SCOL_OFFSET 7 65 66 #define SPI_TMOD_OFFSET 8 67 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) 68 #define SPI_TMOD_TR 0x0 /* xmit & recv */ 69 #define SPI_TMOD_TO 0x1 /* xmit only */ 70 #define SPI_TMOD_RO 0x2 /* recv only */ 71 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ 72 73 #define SPI_SLVOE_OFFSET 10 74 #define SPI_SRL_OFFSET 11 75 #define SPI_CFS_OFFSET 12 76 77 /* Bit fields in SR, 7 bits */ 78 #define SR_MASK GENMASK(6, 0) /* cover 7 bits */ 79 #define SR_BUSY BIT(0) 80 #define SR_TF_NOT_FULL BIT(1) 81 #define SR_TF_EMPT BIT(2) 82 #define SR_RF_NOT_EMPT BIT(3) 83 #define SR_RF_FULL BIT(4) 84 #define SR_TX_ERR BIT(5) 85 #define SR_DCOL BIT(6) 86 87 #define RX_TIMEOUT 1000 /* timeout in ms */ 88 89 struct dw_spi_platdata { 90 s32 frequency; /* Default clock frequency, -1 for none */ 91 void __iomem *regs; 92 }; 93 94 struct dw_spi_priv { 95 void __iomem *regs; 96 unsigned int freq; /* Default frequency */ 97 unsigned int mode; 98 struct clk clk; 99 unsigned long bus_clk_rate; 100 101 struct gpio_desc cs_gpio; /* External chip-select gpio */ 102 103 int bits_per_word; 104 u8 cs; /* chip select pin */ 105 u8 tmode; /* TR/TO/RO/EEPROM */ 106 u8 type; /* SPI/SSP/MicroWire */ 107 int len; 108 109 u32 fifo_len; /* depth of the FIFO buffer */ 110 void *tx; 111 void *tx_end; 112 void *rx; 113 void *rx_end; 114 }; 115 116 static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset) 117 { 118 return __raw_readl(priv->regs + offset); 119 } 120 121 static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val) 122 { 123 __raw_writel(val, priv->regs + offset); 124 } 125 126 static int request_gpio_cs(struct udevice *bus) 127 { 128 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) 129 struct dw_spi_priv *priv = dev_get_priv(bus); 130 int ret; 131 132 /* External chip select gpio line is optional */ 133 ret = gpio_request_by_name(bus, "cs-gpio", 0, &priv->cs_gpio, 0); 134 if (ret == -ENOENT) 135 return 0; 136 137 if (ret < 0) { 138 printf("Error: %d: Can't get %s gpio!\n", ret, bus->name); 139 return ret; 140 } 141 142 if (dm_gpio_is_valid(&priv->cs_gpio)) { 143 dm_gpio_set_dir_flags(&priv->cs_gpio, 144 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 145 } 146 147 debug("%s: used external gpio for CS management\n", __func__); 148 #endif 149 return 0; 150 } 151 152 static int dw_spi_ofdata_to_platdata(struct udevice *bus) 153 { 154 struct dw_spi_platdata *plat = bus->platdata; 155 const void *blob = gd->fdt_blob; 156 int node = dev_of_offset(bus); 157 158 plat->regs = (struct dw_spi *)devfdt_get_addr(bus); 159 160 /* Use 500KHz as a suitable default */ 161 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 162 500000); 163 debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs, 164 plat->frequency); 165 166 return request_gpio_cs(bus); 167 } 168 169 static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable) 170 { 171 dw_write(priv, DW_SPI_SSIENR, (enable ? 1 : 0)); 172 } 173 174 /* Restart the controller, disable all interrupts, clean rx fifo */ 175 static void spi_hw_init(struct dw_spi_priv *priv) 176 { 177 spi_enable_chip(priv, 0); 178 dw_write(priv, DW_SPI_IMR, 0xff); 179 spi_enable_chip(priv, 1); 180 181 /* 182 * Try to detect the FIFO depth if not set by interface driver, 183 * the depth could be from 2 to 256 from HW spec 184 */ 185 if (!priv->fifo_len) { 186 u32 fifo; 187 188 for (fifo = 1; fifo < 256; fifo++) { 189 dw_write(priv, DW_SPI_TXFLTR, fifo); 190 if (fifo != dw_read(priv, DW_SPI_TXFLTR)) 191 break; 192 } 193 194 priv->fifo_len = (fifo == 1) ? 0 : fifo; 195 dw_write(priv, DW_SPI_TXFLTR, 0); 196 } 197 debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); 198 } 199 200 /* 201 * We define dw_spi_get_clk function as 'weak' as some targets 202 * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API 203 * and implement dw_spi_get_clk their own way in their clock manager. 204 */ 205 __weak int dw_spi_get_clk(struct udevice *bus, ulong *rate) 206 { 207 struct dw_spi_priv *priv = dev_get_priv(bus); 208 int ret; 209 210 ret = clk_get_by_index(bus, 0, &priv->clk); 211 if (ret) 212 return ret; 213 214 ret = clk_enable(&priv->clk); 215 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) 216 return ret; 217 218 *rate = clk_get_rate(&priv->clk); 219 if (!*rate) 220 goto err_rate; 221 222 debug("%s: get spi controller clk via device tree: %lu Hz\n", 223 __func__, *rate); 224 225 return 0; 226 227 err_rate: 228 clk_disable(&priv->clk); 229 clk_free(&priv->clk); 230 231 return -EINVAL; 232 } 233 234 static int dw_spi_probe(struct udevice *bus) 235 { 236 struct dw_spi_platdata *plat = dev_get_platdata(bus); 237 struct dw_spi_priv *priv = dev_get_priv(bus); 238 int ret; 239 240 priv->regs = plat->regs; 241 priv->freq = plat->frequency; 242 243 ret = dw_spi_get_clk(bus, &priv->bus_clk_rate); 244 if (ret) 245 return ret; 246 247 /* Currently only bits_per_word == 8 supported */ 248 priv->bits_per_word = 8; 249 250 priv->tmode = 0; /* Tx & Rx */ 251 252 /* Basic HW init */ 253 spi_hw_init(priv); 254 255 return 0; 256 } 257 258 /* Return the max entries we can fill into tx fifo */ 259 static inline u32 tx_max(struct dw_spi_priv *priv) 260 { 261 u32 tx_left, tx_room, rxtx_gap; 262 263 tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3); 264 tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR); 265 266 /* 267 * Another concern is about the tx/rx mismatch, we 268 * thought about using (priv->fifo_len - rxflr - txflr) as 269 * one maximum value for tx, but it doesn't cover the 270 * data which is out of tx/rx fifo and inside the 271 * shift registers. So a control from sw point of 272 * view is taken. 273 */ 274 rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) / 275 (priv->bits_per_word >> 3); 276 277 return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap)); 278 } 279 280 /* Return the max entries we should read out of rx fifo */ 281 static inline u32 rx_max(struct dw_spi_priv *priv) 282 { 283 u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3); 284 285 return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR)); 286 } 287 288 static void dw_writer(struct dw_spi_priv *priv) 289 { 290 u32 max = tx_max(priv); 291 u16 txw = 0; 292 293 while (max--) { 294 /* Set the tx word if the transfer's original "tx" is not null */ 295 if (priv->tx_end - priv->len) { 296 if (priv->bits_per_word == 8) 297 txw = *(u8 *)(priv->tx); 298 else 299 txw = *(u16 *)(priv->tx); 300 } 301 dw_write(priv, DW_SPI_DR, txw); 302 debug("%s: tx=0x%02x\n", __func__, txw); 303 priv->tx += priv->bits_per_word >> 3; 304 } 305 } 306 307 static void dw_reader(struct dw_spi_priv *priv) 308 { 309 u32 max = rx_max(priv); 310 u16 rxw; 311 312 while (max--) { 313 rxw = dw_read(priv, DW_SPI_DR); 314 debug("%s: rx=0x%02x\n", __func__, rxw); 315 316 /* Care about rx if the transfer's original "rx" is not null */ 317 if (priv->rx_end - priv->len) { 318 if (priv->bits_per_word == 8) 319 *(u8 *)(priv->rx) = rxw; 320 else 321 *(u16 *)(priv->rx) = rxw; 322 } 323 priv->rx += priv->bits_per_word >> 3; 324 } 325 } 326 327 static int poll_transfer(struct dw_spi_priv *priv) 328 { 329 do { 330 dw_writer(priv); 331 dw_reader(priv); 332 } while (priv->rx_end > priv->rx); 333 334 return 0; 335 } 336 337 static void external_cs_manage(struct udevice *dev, bool on) 338 { 339 #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD) 340 struct dw_spi_priv *priv = dev_get_priv(dev->parent); 341 342 if (!dm_gpio_is_valid(&priv->cs_gpio)) 343 return; 344 345 dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0); 346 #endif 347 } 348 349 static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, 350 const void *dout, void *din, unsigned long flags) 351 { 352 struct udevice *bus = dev->parent; 353 struct dw_spi_priv *priv = dev_get_priv(bus); 354 const u8 *tx = dout; 355 u8 *rx = din; 356 int ret = 0; 357 u32 cr0 = 0; 358 u32 val; 359 u32 cs; 360 361 /* spi core configured to do 8 bit transfers */ 362 if (bitlen % 8) { 363 debug("Non byte aligned SPI transfer.\n"); 364 return -1; 365 } 366 367 /* Start the transaction if necessary. */ 368 if (flags & SPI_XFER_BEGIN) 369 external_cs_manage(dev, false); 370 371 cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) | 372 (priv->mode << SPI_MODE_OFFSET) | 373 (priv->tmode << SPI_TMOD_OFFSET); 374 375 if (rx && tx) 376 priv->tmode = SPI_TMOD_TR; 377 else if (rx) 378 priv->tmode = SPI_TMOD_RO; 379 else 380 /* 381 * In transmit only mode (SPI_TMOD_TO) input FIFO never gets 382 * any data which breaks our logic in poll_transfer() above. 383 */ 384 priv->tmode = SPI_TMOD_TR; 385 386 cr0 &= ~SPI_TMOD_MASK; 387 cr0 |= (priv->tmode << SPI_TMOD_OFFSET); 388 389 priv->len = bitlen >> 3; 390 debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len); 391 392 priv->tx = (void *)tx; 393 priv->tx_end = priv->tx + priv->len; 394 priv->rx = rx; 395 priv->rx_end = priv->rx + priv->len; 396 397 /* Disable controller before writing control registers */ 398 spi_enable_chip(priv, 0); 399 400 debug("%s: cr0=%08x\n", __func__, cr0); 401 /* Reprogram cr0 only if changed */ 402 if (dw_read(priv, DW_SPI_CTRL0) != cr0) 403 dw_write(priv, DW_SPI_CTRL0, cr0); 404 405 /* 406 * Configure the desired SS (slave select 0...3) in the controller 407 * The DW SPI controller will activate and deactivate this CS 408 * automatically. So no cs_activate() etc is needed in this driver. 409 */ 410 cs = spi_chip_select(dev); 411 dw_write(priv, DW_SPI_SER, 1 << cs); 412 413 /* Enable controller after writing control registers */ 414 spi_enable_chip(priv, 1); 415 416 /* Start transfer in a polling loop */ 417 ret = poll_transfer(priv); 418 419 /* 420 * Wait for current transmit operation to complete. 421 * Otherwise if some data still exists in Tx FIFO it can be 422 * silently flushed, i.e. dropped on disabling of the controller, 423 * which happens when writing 0 to DW_SPI_SSIENR which happens 424 * in the beginning of new transfer. 425 */ 426 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val, 427 (val & SR_TF_EMPT) && !(val & SR_BUSY), 428 RX_TIMEOUT * 1000)) { 429 ret = -ETIMEDOUT; 430 } 431 432 /* Stop the transaction if necessary */ 433 if (flags & SPI_XFER_END) 434 external_cs_manage(dev, true); 435 436 return ret; 437 } 438 439 static int dw_spi_set_speed(struct udevice *bus, uint speed) 440 { 441 struct dw_spi_platdata *plat = bus->platdata; 442 struct dw_spi_priv *priv = dev_get_priv(bus); 443 u16 clk_div; 444 445 if (speed > plat->frequency) 446 speed = plat->frequency; 447 448 /* Disable controller before writing control registers */ 449 spi_enable_chip(priv, 0); 450 451 /* clk_div doesn't support odd number */ 452 clk_div = priv->bus_clk_rate / speed; 453 clk_div = (clk_div + 1) & 0xfffe; 454 dw_write(priv, DW_SPI_BAUDR, clk_div); 455 456 /* Enable controller after writing control registers */ 457 spi_enable_chip(priv, 1); 458 459 priv->freq = speed; 460 debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs, 461 priv->freq, clk_div); 462 463 return 0; 464 } 465 466 static int dw_spi_set_mode(struct udevice *bus, uint mode) 467 { 468 struct dw_spi_priv *priv = dev_get_priv(bus); 469 470 /* 471 * Can't set mode yet. Since this depends on if rx, tx, or 472 * rx & tx is requested. So we have to defer this to the 473 * real transfer function. 474 */ 475 priv->mode = mode; 476 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); 477 478 return 0; 479 } 480 481 static const struct dm_spi_ops dw_spi_ops = { 482 .xfer = dw_spi_xfer, 483 .set_speed = dw_spi_set_speed, 484 .set_mode = dw_spi_set_mode, 485 /* 486 * cs_info is not needed, since we require all chip selects to be 487 * in the device tree explicitly 488 */ 489 }; 490 491 static const struct udevice_id dw_spi_ids[] = { 492 { .compatible = "snps,dw-apb-ssi" }, 493 { } 494 }; 495 496 U_BOOT_DRIVER(dw_spi) = { 497 .name = "dw_spi", 498 .id = UCLASS_SPI, 499 .of_match = dw_spi_ids, 500 .ops = &dw_spi_ops, 501 .ofdata_to_platdata = dw_spi_ofdata_to_platdata, 502 .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata), 503 .priv_auto_alloc_size = sizeof(struct dw_spi_priv), 504 .probe = dw_spi_probe, 505 }; 506
