1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2006 4 * Vipin Kumar, ST Micoelectronics, vipin.kumar (at) st.com. 5 */ 6 7 #include <config.h> 8 9 /* 10 * platform specific initializations are already done in Xloader 11 * Initializations already done include 12 * DDR, PLLs, IP's clock enable and reset release etc 13 */ 14 .globl lowlevel_init 15 lowlevel_init: 16 mov pc, lr 17 18 /* void setfreq(unsigned int device, unsigned int frequency) */ 19 .global setfreq 20 setfreq: 21 stmfd sp!,{r14} 22 stmfd sp!,{r0-r12} 23 24 mov r8,sp 25 ldr sp,SRAM_STACK_V 26 27 /* Saving the function arguements for later use */ 28 mov r4,r0 29 mov r5,r1 30 31 /* Putting DDR into self refresh */ 32 ldr r0,DDR_07_V 33 ldr r1,[r0] 34 ldr r2,DDR_ACTIVE_V 35 bic r1, r1, r2 36 str r1,[r0] 37 ldr r0,DDR_57_V 38 ldr r1,[r0] 39 ldr r2,CYCLES_MASK_V 40 bic r1, r1, r2 41 ldr r2,REFRESH_CYCLES_V 42 orr r1, r1, r2, lsl #16 43 str r1,[r0] 44 ldr r0,DDR_07_V 45 ldr r1,[r0] 46 ldr r2,SREFRESH_MASK_V 47 orr r1, r1, r2 48 str r1,[r0] 49 50 /* flush pipeline */ 51 b flush 52 .align 5 53 flush: 54 /* Delay to ensure self refresh mode */ 55 ldr r0,SREFRESH_DELAY_V 56 delay: 57 sub r0,r0,#1 58 cmp r0,#0 59 bne delay 60 61 /* Putting system in slow mode */ 62 ldr r0,SCCTRL_V 63 mov r1,#2 64 str r1,[r0] 65 66 /* Changing PLL(1/2) frequency */ 67 mov r0,r4 68 mov r1,r5 69 70 cmp r4,#0 71 beq pll1_freq 72 73 /* Change PLL2 (DDR frequency) */ 74 ldr r6,PLL2_FREQ_V 75 ldr r7,PLL2_CNTL_V 76 b pll2_freq 77 78 pll1_freq: 79 /* Change PLL1 (CPU frequency) */ 80 ldr r6,PLL1_FREQ_V 81 ldr r7,PLL1_CNTL_V 82 83 pll2_freq: 84 mov r0,r6 85 ldr r1,[r0] 86 ldr r2,PLLFREQ_MASK_V 87 bic r1,r1,r2 88 mov r2,r5,lsr#1 89 orr r1,r1,r2,lsl#24 90 str r1,[r0] 91 92 mov r0,r7 93 ldr r1,P1C0A_V 94 str r1,[r0] 95 ldr r1,P1C0E_V 96 str r1,[r0] 97 ldr r1,P1C06_V 98 str r1,[r0] 99 ldr r1,P1C0E_V 100 str r1,[r0] 101 102 lock: 103 ldr r1,[r0] 104 and r1,r1,#1 105 cmp r1,#0 106 beq lock 107 108 /* Putting system back to normal mode */ 109 ldr r0,SCCTRL_V 110 mov r1,#4 111 str r1,[r0] 112 113 /* Putting DDR back to normal */ 114 ldr r0,DDR_07_V 115 ldr r1,[R0] 116 ldr r2,SREFRESH_MASK_V 117 bic r1, r1, r2 118 str r1,[r0] 119 ldr r2,DDR_ACTIVE_V 120 orr r1, r1, r2 121 str r1,[r0] 122 123 /* Delay to ensure self refresh mode */ 124 ldr r0,SREFRESH_DELAY_V 125 1: 126 sub r0,r0,#1 127 cmp r0,#0 128 bne 1b 129 130 mov sp,r8 131 /* Resuming back to code */ 132 ldmia sp!,{r0-r12} 133 ldmia sp!,{pc} 134 135 SCCTRL_V: 136 .word 0xfca00000 137 PLL1_FREQ_V: 138 .word 0xfca8000C 139 PLL1_CNTL_V: 140 .word 0xfca80008 141 PLL2_FREQ_V: 142 .word 0xfca80018 143 PLL2_CNTL_V: 144 .word 0xfca80014 145 PLLFREQ_MASK_V: 146 .word 0xff000000 147 P1C0A_V: 148 .word 0x1C0A 149 P1C0E_V: 150 .word 0x1C0E 151 P1C06_V: 152 .word 0x1C06 153 154 SREFRESH_DELAY_V: 155 .word 0x9999 156 SRAM_STACK_V: 157 .word 0xD2800600 158 DDR_07_V: 159 .word 0xfc60001c 160 DDR_ACTIVE_V: 161 .word 0x01000000 162 DDR_57_V: 163 .word 0xfc6000e4 164 CYCLES_MASK_V: 165 .word 0xffff0000 166 REFRESH_CYCLES_V: 167 .word 0xf0f0 168 SREFRESH_MASK_V: 169 .word 0x00010000 170 171 .global setfreq_sz 172 setfreq_sz: 173 .word setfreq_sz - setfreq 174
