1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * USB HOST XHCI Controller stack 4 * 5 * Based on xHCI host controller driver in linux-kernel 6 * by Sarah Sharp. 7 * 8 * Copyright (C) 2008 Intel Corp. 9 * Author: Sarah Sharp 10 * 11 * Copyright (C) 2013 Samsung Electronics Co.Ltd 12 * Authors: Vivek Gautam <gautam.vivek (at) samsung.com> 13 * Vikas Sajjan <vikas.sajjan (at) samsung.com> 14 */ 15 16 /** 17 * This file gives the xhci stack for usb3.0 looking into 18 * xhci specification Rev1.0 (5/21/10). 19 * The quirk devices support hasn't been given yet. 20 */ 21 22 #include <common.h> 23 #include <dm.h> 24 #include <asm/byteorder.h> 25 #include <usb.h> 26 #include <malloc.h> 27 #include <watchdog.h> 28 #include <asm/cache.h> 29 #include <asm/unaligned.h> 30 #include <linux/errno.h> 31 #include "xhci.h" 32 33 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT 34 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 35 #endif 36 37 static struct descriptor { 38 struct usb_hub_descriptor hub; 39 struct usb_device_descriptor device; 40 struct usb_config_descriptor config; 41 struct usb_interface_descriptor interface; 42 struct usb_endpoint_descriptor endpoint; 43 struct usb_ss_ep_comp_descriptor ep_companion; 44 } __attribute__ ((packed)) descriptor = { 45 { 46 0xc, /* bDescLength */ 47 0x2a, /* bDescriptorType: hub descriptor */ 48 2, /* bNrPorts -- runtime modified */ 49 cpu_to_le16(0x8), /* wHubCharacteristics */ 50 10, /* bPwrOn2PwrGood */ 51 0, /* bHubCntrCurrent */ 52 { /* Device removable */ 53 } /* at most 7 ports! XXX */ 54 }, 55 { 56 0x12, /* bLength */ 57 1, /* bDescriptorType: UDESC_DEVICE */ 58 cpu_to_le16(0x0300), /* bcdUSB: v3.0 */ 59 9, /* bDeviceClass: UDCLASS_HUB */ 60 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ 61 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */ 62 9, /* bMaxPacketSize: 512 bytes 2^9 */ 63 0x0000, /* idVendor */ 64 0x0000, /* idProduct */ 65 cpu_to_le16(0x0100), /* bcdDevice */ 66 1, /* iManufacturer */ 67 2, /* iProduct */ 68 0, /* iSerialNumber */ 69 1 /* bNumConfigurations: 1 */ 70 }, 71 { 72 0x9, 73 2, /* bDescriptorType: UDESC_CONFIG */ 74 cpu_to_le16(0x1f), /* includes SS endpoint descriptor */ 75 1, /* bNumInterface */ 76 1, /* bConfigurationValue */ 77 0, /* iConfiguration */ 78 0x40, /* bmAttributes: UC_SELF_POWER */ 79 0 /* bMaxPower */ 80 }, 81 { 82 0x9, /* bLength */ 83 4, /* bDescriptorType: UDESC_INTERFACE */ 84 0, /* bInterfaceNumber */ 85 0, /* bAlternateSetting */ 86 1, /* bNumEndpoints */ 87 9, /* bInterfaceClass: UICLASS_HUB */ 88 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ 89 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ 90 0 /* iInterface */ 91 }, 92 { 93 0x7, /* bLength */ 94 5, /* bDescriptorType: UDESC_ENDPOINT */ 95 0x81, /* bEndpointAddress: IN endpoint 1 */ 96 3, /* bmAttributes: UE_INTERRUPT */ 97 8, /* wMaxPacketSize */ 98 255 /* bInterval */ 99 }, 100 { 101 0x06, /* ss_bLength */ 102 0x30, /* ss_bDescriptorType: SS EP Companion */ 103 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */ 104 /* ss_bmAttributes: 1 packet per service interval */ 105 0x00, 106 /* ss_wBytesPerInterval: 15 bits for max 15 ports */ 107 cpu_to_le16(0x02), 108 }, 109 }; 110 111 #ifndef CONFIG_DM_USB 112 static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; 113 #endif 114 115 struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev) 116 { 117 #ifdef CONFIG_DM_USB 118 struct udevice *dev; 119 120 /* Find the USB controller */ 121 for (dev = udev->dev; 122 device_get_uclass_id(dev) != UCLASS_USB; 123 dev = dev->parent) 124 ; 125 return dev_get_priv(dev); 126 #else 127 return udev->controller; 128 #endif 129 } 130 131 /** 132 * Waits for as per specified amount of time 133 * for the "result" to match with "done" 134 * 135 * @param ptr pointer to the register to be read 136 * @param mask mask for the value read 137 * @param done value to be campared with result 138 * @param usec time to wait till 139 * @return 0 if handshake is success else < 0 on failure 140 */ 141 static int handshake(uint32_t volatile *ptr, uint32_t mask, 142 uint32_t done, int usec) 143 { 144 uint32_t result; 145 146 do { 147 result = xhci_readl(ptr); 148 if (result == ~(uint32_t)0) 149 return -ENODEV; 150 result &= mask; 151 if (result == done) 152 return 0; 153 usec--; 154 udelay(1); 155 } while (usec > 0); 156 157 return -ETIMEDOUT; 158 } 159 160 /** 161 * Set the run bit and wait for the host to be running. 162 * 163 * @param hcor pointer to host controller operation registers 164 * @return status of the Handshake 165 */ 166 static int xhci_start(struct xhci_hcor *hcor) 167 { 168 u32 temp; 169 int ret; 170 171 puts("Starting the controller\n"); 172 temp = xhci_readl(&hcor->or_usbcmd); 173 temp |= (CMD_RUN); 174 xhci_writel(&hcor->or_usbcmd, temp); 175 176 /* 177 * Wait for the HCHalted Status bit to be 0 to indicate the host is 178 * running. 179 */ 180 ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC); 181 if (ret) 182 debug("Host took too long to start, " 183 "waited %u microseconds.\n", 184 XHCI_MAX_HALT_USEC); 185 return ret; 186 } 187 188 /** 189 * Resets the XHCI Controller 190 * 191 * @param hcor pointer to host controller operation registers 192 * @return -EBUSY if XHCI Controller is not halted else status of handshake 193 */ 194 static int xhci_reset(struct xhci_hcor *hcor) 195 { 196 u32 cmd; 197 u32 state; 198 int ret; 199 200 /* Halting the Host first */ 201 debug("// Halt the HC: %p\n", hcor); 202 state = xhci_readl(&hcor->or_usbsts) & STS_HALT; 203 if (!state) { 204 cmd = xhci_readl(&hcor->or_usbcmd); 205 cmd &= ~CMD_RUN; 206 xhci_writel(&hcor->or_usbcmd, cmd); 207 } 208 209 ret = handshake(&hcor->or_usbsts, 210 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); 211 if (ret) { 212 printf("Host not halted after %u microseconds.\n", 213 XHCI_MAX_HALT_USEC); 214 return -EBUSY; 215 } 216 217 debug("// Reset the HC\n"); 218 cmd = xhci_readl(&hcor->or_usbcmd); 219 cmd |= CMD_RESET; 220 xhci_writel(&hcor->or_usbcmd, cmd); 221 222 ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC); 223 if (ret) 224 return ret; 225 226 /* 227 * xHCI cannot write to any doorbells or operational registers other 228 * than status until the "Controller Not Ready" flag is cleared. 229 */ 230 return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC); 231 } 232 233 /** 234 * Used for passing endpoint bitmasks between the core and HCDs. 235 * Find the index for an endpoint given its descriptor. 236 * Use the return value to right shift 1 for the bitmask. 237 * 238 * Index = (epnum * 2) + direction - 1, 239 * where direction = 0 for OUT, 1 for IN. 240 * For control endpoints, the IN index is used (OUT index is unused), so 241 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) 242 * 243 * @param desc USB enpdoint Descriptor 244 * @return index of the Endpoint 245 */ 246 static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc) 247 { 248 unsigned int index; 249 250 if (usb_endpoint_xfer_control(desc)) 251 index = (unsigned int)(usb_endpoint_num(desc) * 2); 252 else 253 index = (unsigned int)((usb_endpoint_num(desc) * 2) - 254 (usb_endpoint_dir_in(desc) ? 0 : 1)); 255 256 return index; 257 } 258 259 /* 260 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of 261 * microframes, rounded down to nearest power of 2. 262 */ 263 static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval, 264 unsigned int min_exponent, 265 unsigned int max_exponent) 266 { 267 unsigned int interval; 268 269 interval = fls(desc_interval) - 1; 270 interval = clamp_val(interval, min_exponent, max_exponent); 271 if ((1 << interval) != desc_interval) 272 debug("rounding interval to %d microframes, "\ 273 "ep desc says %d microframes\n", 274 1 << interval, desc_interval); 275 276 return interval; 277 } 278 279 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev, 280 struct usb_endpoint_descriptor *endpt_desc) 281 { 282 if (endpt_desc->bInterval == 0) 283 return 0; 284 285 return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15); 286 } 287 288 static unsigned int xhci_parse_frame_interval(struct usb_device *udev, 289 struct usb_endpoint_descriptor *endpt_desc) 290 { 291 return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10); 292 } 293 294 /* 295 * Convert interval expressed as 2^(bInterval - 1) == interval into 296 * straight exponent value 2^n == interval. 297 */ 298 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev, 299 struct usb_endpoint_descriptor *endpt_desc) 300 { 301 unsigned int interval; 302 303 interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1; 304 if (interval != endpt_desc->bInterval - 1) 305 debug("ep %#x - rounding interval to %d %sframes\n", 306 endpt_desc->bEndpointAddress, 1 << interval, 307 udev->speed == USB_SPEED_FULL ? "" : "micro"); 308 309 if (udev->speed == USB_SPEED_FULL) { 310 /* 311 * Full speed isoc endpoints specify interval in frames, 312 * not microframes. We are using microframes everywhere, 313 * so adjust accordingly. 314 */ 315 interval += 3; /* 1 frame = 2^3 uframes */ 316 } 317 318 return interval; 319 } 320 321 /* 322 * Return the polling or NAK interval. 323 * 324 * The polling interval is expressed in "microframes". If xHCI's Interval field 325 * is set to N, it will service the endpoint every 2^(Interval)*125us. 326 * 327 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval 328 * is set to 0. 329 */ 330 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev, 331 struct usb_endpoint_descriptor *endpt_desc) 332 { 333 unsigned int interval = 0; 334 335 switch (udev->speed) { 336 case USB_SPEED_HIGH: 337 /* Max NAK rate */ 338 if (usb_endpoint_xfer_control(endpt_desc) || 339 usb_endpoint_xfer_bulk(endpt_desc)) { 340 interval = xhci_parse_microframe_interval(udev, 341 endpt_desc); 342 break; 343 } 344 /* Fall through - SS and HS isoc/int have same decoding */ 345 346 case USB_SPEED_SUPER: 347 if (usb_endpoint_xfer_int(endpt_desc) || 348 usb_endpoint_xfer_isoc(endpt_desc)) { 349 interval = xhci_parse_exponent_interval(udev, 350 endpt_desc); 351 } 352 break; 353 354 case USB_SPEED_FULL: 355 if (usb_endpoint_xfer_isoc(endpt_desc)) { 356 interval = xhci_parse_exponent_interval(udev, 357 endpt_desc); 358 break; 359 } 360 /* 361 * Fall through for interrupt endpoint interval decoding 362 * since it uses the same rules as low speed interrupt 363 * endpoints. 364 */ 365 366 case USB_SPEED_LOW: 367 if (usb_endpoint_xfer_int(endpt_desc) || 368 usb_endpoint_xfer_isoc(endpt_desc)) { 369 interval = xhci_parse_frame_interval(udev, endpt_desc); 370 } 371 break; 372 373 default: 374 BUG(); 375 } 376 377 return interval; 378 } 379 380 /* 381 * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps. 382 * High speed endpoint descriptors can define "the number of additional 383 * transaction opportunities per microframe", but that goes in the Max Burst 384 * endpoint context field. 385 */ 386 static u32 xhci_get_endpoint_mult(struct usb_device *udev, 387 struct usb_endpoint_descriptor *endpt_desc, 388 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc) 389 { 390 if (udev->speed < USB_SPEED_SUPER || 391 !usb_endpoint_xfer_isoc(endpt_desc)) 392 return 0; 393 394 return ss_ep_comp_desc->bmAttributes; 395 } 396 397 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev, 398 struct usb_endpoint_descriptor *endpt_desc, 399 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc) 400 { 401 /* Super speed and Plus have max burst in ep companion desc */ 402 if (udev->speed >= USB_SPEED_SUPER) 403 return ss_ep_comp_desc->bMaxBurst; 404 405 if (udev->speed == USB_SPEED_HIGH && 406 (usb_endpoint_xfer_isoc(endpt_desc) || 407 usb_endpoint_xfer_int(endpt_desc))) 408 return usb_endpoint_maxp_mult(endpt_desc) - 1; 409 410 return 0; 411 } 412 413 /* 414 * Return the maximum endpoint service interval time (ESIT) payload. 415 * Basically, this is the maxpacket size, multiplied by the burst size 416 * and mult size. 417 */ 418 static u32 xhci_get_max_esit_payload(struct usb_device *udev, 419 struct usb_endpoint_descriptor *endpt_desc, 420 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc) 421 { 422 int max_burst; 423 int max_packet; 424 425 /* Only applies for interrupt or isochronous endpoints */ 426 if (usb_endpoint_xfer_control(endpt_desc) || 427 usb_endpoint_xfer_bulk(endpt_desc)) 428 return 0; 429 430 /* SuperSpeed Isoc ep with less than 48k per esit */ 431 if (udev->speed >= USB_SPEED_SUPER) 432 return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval); 433 434 max_packet = usb_endpoint_maxp(endpt_desc); 435 max_burst = usb_endpoint_maxp_mult(endpt_desc); 436 437 /* A 0 in max burst means 1 transfer per ESIT */ 438 return max_packet * max_burst; 439 } 440 441 /** 442 * Issue a configure endpoint command or evaluate context command 443 * and wait for it to finish. 444 * 445 * @param udev pointer to the Device Data Structure 446 * @param ctx_change flag to indicate the Context has changed or NOT 447 * @return 0 on success, -1 on failure 448 */ 449 static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change) 450 { 451 struct xhci_container_ctx *in_ctx; 452 struct xhci_virt_device *virt_dev; 453 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 454 union xhci_trb *event; 455 456 virt_dev = ctrl->devs[udev->slot_id]; 457 in_ctx = virt_dev->in_ctx; 458 459 xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size); 460 xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0, 461 ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP); 462 event = xhci_wait_for_event(ctrl, TRB_COMPLETION); 463 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) 464 != udev->slot_id); 465 466 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) { 467 case COMP_SUCCESS: 468 debug("Successful %s command\n", 469 ctx_change ? "Evaluate Context" : "Configure Endpoint"); 470 break; 471 default: 472 printf("ERROR: %s command returned completion code %d.\n", 473 ctx_change ? "Evaluate Context" : "Configure Endpoint", 474 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))); 475 return -EINVAL; 476 } 477 478 xhci_acknowledge_event(ctrl); 479 480 return 0; 481 } 482 483 /** 484 * Configure the endpoint, programming the device contexts. 485 * 486 * @param udev pointer to the USB device structure 487 * @return returns the status of the xhci_configure_endpoints 488 */ 489 static int xhci_set_configuration(struct usb_device *udev) 490 { 491 struct xhci_container_ctx *in_ctx; 492 struct xhci_container_ctx *out_ctx; 493 struct xhci_input_control_ctx *ctrl_ctx; 494 struct xhci_slot_ctx *slot_ctx; 495 struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM]; 496 int cur_ep; 497 int max_ep_flag = 0; 498 int ep_index; 499 unsigned int dir; 500 unsigned int ep_type; 501 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 502 int num_of_ep; 503 int ep_flag = 0; 504 u64 trb_64 = 0; 505 int slot_id = udev->slot_id; 506 struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; 507 struct usb_interface *ifdesc; 508 u32 max_esit_payload; 509 unsigned int interval; 510 unsigned int mult; 511 unsigned int max_burst; 512 unsigned int avg_trb_len; 513 unsigned int err_count = 0; 514 515 out_ctx = virt_dev->out_ctx; 516 in_ctx = virt_dev->in_ctx; 517 518 num_of_ep = udev->config.if_desc[0].no_of_ep; 519 ifdesc = &udev->config.if_desc[0]; 520 521 ctrl_ctx = xhci_get_input_control_ctx(in_ctx); 522 /* Initialize the input context control */ 523 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); 524 ctrl_ctx->drop_flags = 0; 525 526 /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */ 527 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) { 528 ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]); 529 ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1)); 530 if (max_ep_flag < ep_flag) 531 max_ep_flag = ep_flag; 532 } 533 534 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size); 535 536 /* slot context */ 537 xhci_slot_copy(ctrl, in_ctx, out_ctx); 538 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); 539 slot_ctx->dev_info &= ~(cpu_to_le32(LAST_CTX_MASK)); 540 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0); 541 542 xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0); 543 544 /* filling up ep contexts */ 545 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) { 546 struct usb_endpoint_descriptor *endpt_desc = NULL; 547 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL; 548 549 endpt_desc = &ifdesc->ep_desc[cur_ep]; 550 ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep]; 551 trb_64 = 0; 552 553 /* 554 * Get values to fill the endpoint context, mostly from ep 555 * descriptor. The average TRB buffer lengt for bulk endpoints 556 * is unclear as we have no clue on scatter gather list entry 557 * size. For Isoc and Int, set it to max available. 558 * See xHCI 1.1 spec 4.14.1.1 for details. 559 */ 560 max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc, 561 ss_ep_comp_desc); 562 interval = xhci_get_endpoint_interval(udev, endpt_desc); 563 mult = xhci_get_endpoint_mult(udev, endpt_desc, 564 ss_ep_comp_desc); 565 max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc, 566 ss_ep_comp_desc); 567 avg_trb_len = max_esit_payload; 568 569 ep_index = xhci_get_ep_index(endpt_desc); 570 ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); 571 572 /* Allocate the ep rings */ 573 virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true); 574 if (!virt_dev->eps[ep_index].ring) 575 return -ENOMEM; 576 577 /*NOTE: ep_desc[0] actually represents EP1 and so on */ 578 dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7); 579 ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2)); 580 581 ep_ctx[ep_index]->ep_info = 582 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) | 583 EP_INTERVAL(interval) | EP_MULT(mult)); 584 585 ep_ctx[ep_index]->ep_info2 = 586 cpu_to_le32(ep_type << EP_TYPE_SHIFT); 587 ep_ctx[ep_index]->ep_info2 |= 588 cpu_to_le32(MAX_PACKET 589 (get_unaligned(&endpt_desc->wMaxPacketSize))); 590 591 /* Allow 3 retries for everything but isoc, set CErr = 3 */ 592 if (!usb_endpoint_xfer_isoc(endpt_desc)) 593 err_count = 3; 594 ep_ctx[ep_index]->ep_info2 |= 595 cpu_to_le32(MAX_BURST(max_burst) | 596 ERROR_COUNT(err_count)); 597 598 trb_64 = (uintptr_t) 599 virt_dev->eps[ep_index].ring->enqueue; 600 ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 | 601 virt_dev->eps[ep_index].ring->cycle_state); 602 603 /* 604 * xHCI spec 6.2.3: 605 * 'Average TRB Length' should be 8 for control endpoints. 606 */ 607 if (usb_endpoint_xfer_control(endpt_desc)) 608 avg_trb_len = 8; 609 ep_ctx[ep_index]->tx_info = 610 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) | 611 EP_AVG_TRB_LENGTH(avg_trb_len)); 612 } 613 614 return xhci_configure_endpoints(udev, false); 615 } 616 617 /** 618 * Issue an Address Device command (which will issue a SetAddress request to 619 * the device). 620 * 621 * @param udev pointer to the Device Data Structure 622 * @return 0 if successful else error code on failure 623 */ 624 static int xhci_address_device(struct usb_device *udev, int root_portnr) 625 { 626 int ret = 0; 627 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 628 struct xhci_slot_ctx *slot_ctx; 629 struct xhci_input_control_ctx *ctrl_ctx; 630 struct xhci_virt_device *virt_dev; 631 int slot_id = udev->slot_id; 632 union xhci_trb *event; 633 634 virt_dev = ctrl->devs[slot_id]; 635 636 /* 637 * This is the first Set Address since device plug-in 638 * so setting up the slot context. 639 */ 640 debug("Setting up addressable devices %p\n", ctrl->dcbaa); 641 xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr); 642 643 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); 644 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); 645 ctrl_ctx->drop_flags = 0; 646 647 xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV); 648 event = xhci_wait_for_event(ctrl, TRB_COMPLETION); 649 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id); 650 651 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) { 652 case COMP_CTX_STATE: 653 case COMP_EBADSLT: 654 printf("Setup ERROR: address device command for slot %d.\n", 655 slot_id); 656 ret = -EINVAL; 657 break; 658 case COMP_TX_ERR: 659 puts("Device not responding to set address.\n"); 660 ret = -EPROTO; 661 break; 662 case COMP_DEV_ERR: 663 puts("ERROR: Incompatible device" 664 "for address device command.\n"); 665 ret = -ENODEV; 666 break; 667 case COMP_SUCCESS: 668 debug("Successful Address Device command\n"); 669 udev->status = 0; 670 break; 671 default: 672 printf("ERROR: unexpected command completion code 0x%x.\n", 673 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))); 674 ret = -EINVAL; 675 break; 676 } 677 678 xhci_acknowledge_event(ctrl); 679 680 if (ret < 0) 681 /* 682 * TODO: Unsuccessful Address Device command shall leave the 683 * slot in default state. So, issue Disable Slot command now. 684 */ 685 return ret; 686 687 xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes, 688 virt_dev->out_ctx->size); 689 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx); 690 691 debug("xHC internal address is: %d\n", 692 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); 693 694 return 0; 695 } 696 697 /** 698 * Issue Enable slot command to the controller to allocate 699 * device slot and assign the slot id. It fails if the xHC 700 * ran out of device slots, the Enable Slot command timed out, 701 * or allocating memory failed. 702 * 703 * @param udev pointer to the Device Data Structure 704 * @return Returns 0 on succes else return error code on failure 705 */ 706 static int _xhci_alloc_device(struct usb_device *udev) 707 { 708 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 709 union xhci_trb *event; 710 int ret; 711 712 /* 713 * Root hub will be first device to be initailized. 714 * If this device is root-hub, don't do any xHC related 715 * stuff. 716 */ 717 if (ctrl->rootdev == 0) { 718 udev->speed = USB_SPEED_SUPER; 719 return 0; 720 } 721 722 xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT); 723 event = xhci_wait_for_event(ctrl, TRB_COMPLETION); 724 BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)) 725 != COMP_SUCCESS); 726 727 udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)); 728 729 xhci_acknowledge_event(ctrl); 730 731 ret = xhci_alloc_virt_device(ctrl, udev->slot_id); 732 if (ret < 0) { 733 /* 734 * TODO: Unsuccessful Address Device command shall leave 735 * the slot in default. So, issue Disable Slot command now. 736 */ 737 puts("Could not allocate xHCI USB device data structures\n"); 738 return ret; 739 } 740 741 return 0; 742 } 743 744 #ifndef CONFIG_DM_USB 745 int usb_alloc_device(struct usb_device *udev) 746 { 747 return _xhci_alloc_device(udev); 748 } 749 #endif 750 751 /* 752 * Full speed devices may have a max packet size greater than 8 bytes, but the 753 * USB core doesn't know that until it reads the first 8 bytes of the 754 * descriptor. If the usb_device's max packet size changes after that point, 755 * we need to issue an evaluate context command and wait on it. 756 * 757 * @param udev pointer to the Device Data Structure 758 * @return returns the status of the xhci_configure_endpoints 759 */ 760 int xhci_check_maxpacket(struct usb_device *udev) 761 { 762 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 763 unsigned int slot_id = udev->slot_id; 764 int ep_index = 0; /* control endpoint */ 765 struct xhci_container_ctx *in_ctx; 766 struct xhci_container_ctx *out_ctx; 767 struct xhci_input_control_ctx *ctrl_ctx; 768 struct xhci_ep_ctx *ep_ctx; 769 int max_packet_size; 770 int hw_max_packet_size; 771 int ret = 0; 772 773 out_ctx = ctrl->devs[slot_id]->out_ctx; 774 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size); 775 776 ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index); 777 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); 778 max_packet_size = udev->epmaxpacketin[0]; 779 if (hw_max_packet_size != max_packet_size) { 780 debug("Max Packet Size for ep 0 changed.\n"); 781 debug("Max packet size in usb_device = %d\n", max_packet_size); 782 debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size); 783 debug("Issuing evaluate context command.\n"); 784 785 /* Set up the modified control endpoint 0 */ 786 xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx, 787 ctrl->devs[slot_id]->out_ctx, ep_index); 788 in_ctx = ctrl->devs[slot_id]->in_ctx; 789 ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); 790 ep_ctx->ep_info2 &= cpu_to_le32(~((0xffff & MAX_PACKET_MASK) 791 << MAX_PACKET_SHIFT)); 792 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); 793 794 /* 795 * Set up the input context flags for the command 796 * FIXME: This won't work if a non-default control endpoint 797 * changes max packet sizes. 798 */ 799 ctrl_ctx = xhci_get_input_control_ctx(in_ctx); 800 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); 801 ctrl_ctx->drop_flags = 0; 802 803 ret = xhci_configure_endpoints(udev, true); 804 } 805 return ret; 806 } 807 808 /** 809 * Clears the Change bits of the Port Status Register 810 * 811 * @param wValue request value 812 * @param wIndex request index 813 * @param addr address of posrt status register 814 * @param port_status state of port status register 815 * @return none 816 */ 817 static void xhci_clear_port_change_bit(u16 wValue, 818 u16 wIndex, volatile uint32_t *addr, u32 port_status) 819 { 820 char *port_change_bit; 821 u32 status; 822 823 switch (wValue) { 824 case USB_PORT_FEAT_C_RESET: 825 status = PORT_RC; 826 port_change_bit = "reset"; 827 break; 828 case USB_PORT_FEAT_C_CONNECTION: 829 status = PORT_CSC; 830 port_change_bit = "connect"; 831 break; 832 case USB_PORT_FEAT_C_OVER_CURRENT: 833 status = PORT_OCC; 834 port_change_bit = "over-current"; 835 break; 836 case USB_PORT_FEAT_C_ENABLE: 837 status = PORT_PEC; 838 port_change_bit = "enable/disable"; 839 break; 840 case USB_PORT_FEAT_C_SUSPEND: 841 status = PORT_PLC; 842 port_change_bit = "suspend/resume"; 843 break; 844 default: 845 /* Should never happen */ 846 return; 847 } 848 849 /* Change bits are all write 1 to clear */ 850 xhci_writel(addr, port_status | status); 851 852 port_status = xhci_readl(addr); 853 debug("clear port %s change, actual port %d status = 0x%x\n", 854 port_change_bit, wIndex, port_status); 855 } 856 857 /** 858 * Save Read Only (RO) bits and save read/write bits where 859 * writing a 0 clears the bit and writing a 1 sets the bit (RWS). 860 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect. 861 * 862 * @param state state of the Port Status and Control Regsiter 863 * @return a value that would result in the port being in the 864 * same state, if the value was written to the port 865 * status control register. 866 */ 867 static u32 xhci_port_state_to_neutral(u32 state) 868 { 869 /* Save read-only status and port state */ 870 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS); 871 } 872 873 /** 874 * Submits the Requests to the XHCI Host Controller 875 * 876 * @param udev pointer to the USB device structure 877 * @param pipe contains the DIR_IN or OUT , devnum 878 * @param buffer buffer to be read/written based on the request 879 * @return returns 0 if successful else -1 on failure 880 */ 881 static int xhci_submit_root(struct usb_device *udev, unsigned long pipe, 882 void *buffer, struct devrequest *req) 883 { 884 uint8_t tmpbuf[4]; 885 u16 typeReq; 886 void *srcptr = NULL; 887 int len, srclen; 888 uint32_t reg; 889 volatile uint32_t *status_reg; 890 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 891 struct xhci_hccr *hccr = ctrl->hccr; 892 struct xhci_hcor *hcor = ctrl->hcor; 893 int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1)); 894 895 if ((req->requesttype & USB_RT_PORT) && 896 le16_to_cpu(req->index) > max_ports) { 897 printf("The request port(%d) exceeds maximum port number\n", 898 le16_to_cpu(req->index) - 1); 899 return -EINVAL; 900 } 901 902 status_reg = (volatile uint32_t *) 903 (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc); 904 srclen = 0; 905 906 typeReq = req->request | req->requesttype << 8; 907 908 switch (typeReq) { 909 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 910 switch (le16_to_cpu(req->value) >> 8) { 911 case USB_DT_DEVICE: 912 debug("USB_DT_DEVICE request\n"); 913 srcptr = &descriptor.device; 914 srclen = 0x12; 915 break; 916 case USB_DT_CONFIG: 917 debug("USB_DT_CONFIG config\n"); 918 srcptr = &descriptor.config; 919 srclen = 0x19; 920 break; 921 case USB_DT_STRING: 922 debug("USB_DT_STRING config\n"); 923 switch (le16_to_cpu(req->value) & 0xff) { 924 case 0: /* Language */ 925 srcptr = "\4\3\11\4"; 926 srclen = 4; 927 break; 928 case 1: /* Vendor String */ 929 srcptr = "\16\3U\0-\0B\0o\0o\0t\0"; 930 srclen = 14; 931 break; 932 case 2: /* Product Name */ 933 srcptr = "\52\3X\0H\0C\0I\0 " 934 "\0H\0o\0s\0t\0 " 935 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; 936 srclen = 42; 937 break; 938 default: 939 printf("unknown value DT_STRING %x\n", 940 le16_to_cpu(req->value)); 941 goto unknown; 942 } 943 break; 944 default: 945 printf("unknown value %x\n", le16_to_cpu(req->value)); 946 goto unknown; 947 } 948 break; 949 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): 950 switch (le16_to_cpu(req->value) >> 8) { 951 case USB_DT_HUB: 952 case USB_DT_SS_HUB: 953 debug("USB_DT_HUB config\n"); 954 srcptr = &descriptor.hub; 955 srclen = 0x8; 956 break; 957 default: 958 printf("unknown value %x\n", le16_to_cpu(req->value)); 959 goto unknown; 960 } 961 break; 962 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): 963 debug("USB_REQ_SET_ADDRESS\n"); 964 ctrl->rootdev = le16_to_cpu(req->value); 965 break; 966 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 967 /* Do nothing */ 968 break; 969 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): 970 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ 971 tmpbuf[1] = 0; 972 srcptr = tmpbuf; 973 srclen = 2; 974 break; 975 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): 976 memset(tmpbuf, 0, 4); 977 reg = xhci_readl(status_reg); 978 if (reg & PORT_CONNECT) { 979 tmpbuf[0] |= USB_PORT_STAT_CONNECTION; 980 switch (reg & DEV_SPEED_MASK) { 981 case XDEV_FS: 982 debug("SPEED = FULLSPEED\n"); 983 break; 984 case XDEV_LS: 985 debug("SPEED = LOWSPEED\n"); 986 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; 987 break; 988 case XDEV_HS: 989 debug("SPEED = HIGHSPEED\n"); 990 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; 991 break; 992 case XDEV_SS: 993 debug("SPEED = SUPERSPEED\n"); 994 tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8; 995 break; 996 } 997 } 998 if (reg & PORT_PE) 999 tmpbuf[0] |= USB_PORT_STAT_ENABLE; 1000 if ((reg & PORT_PLS_MASK) == XDEV_U3) 1001 tmpbuf[0] |= USB_PORT_STAT_SUSPEND; 1002 if (reg & PORT_OC) 1003 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; 1004 if (reg & PORT_RESET) 1005 tmpbuf[0] |= USB_PORT_STAT_RESET; 1006 if (reg & PORT_POWER) 1007 /* 1008 * XXX: This Port power bit (for USB 3.0 hub) 1009 * we are faking in USB 2.0 hub port status; 1010 * since there's a change in bit positions in 1011 * two: 1012 * USB 2.0 port status PP is at position[8] 1013 * USB 3.0 port status PP is at position[9] 1014 * So, we are still keeping it at position [8] 1015 */ 1016 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; 1017 if (reg & PORT_CSC) 1018 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; 1019 if (reg & PORT_PEC) 1020 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; 1021 if (reg & PORT_OCC) 1022 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; 1023 if (reg & PORT_RC) 1024 tmpbuf[2] |= USB_PORT_STAT_C_RESET; 1025 1026 srcptr = tmpbuf; 1027 srclen = 4; 1028 break; 1029 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 1030 reg = xhci_readl(status_reg); 1031 reg = xhci_port_state_to_neutral(reg); 1032 switch (le16_to_cpu(req->value)) { 1033 case USB_PORT_FEAT_ENABLE: 1034 reg |= PORT_PE; 1035 xhci_writel(status_reg, reg); 1036 break; 1037 case USB_PORT_FEAT_POWER: 1038 reg |= PORT_POWER; 1039 xhci_writel(status_reg, reg); 1040 break; 1041 case USB_PORT_FEAT_RESET: 1042 reg |= PORT_RESET; 1043 xhci_writel(status_reg, reg); 1044 break; 1045 default: 1046 printf("unknown feature %x\n", le16_to_cpu(req->value)); 1047 goto unknown; 1048 } 1049 break; 1050 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): 1051 reg = xhci_readl(status_reg); 1052 reg = xhci_port_state_to_neutral(reg); 1053 switch (le16_to_cpu(req->value)) { 1054 case USB_PORT_FEAT_ENABLE: 1055 reg &= ~PORT_PE; 1056 break; 1057 case USB_PORT_FEAT_POWER: 1058 reg &= ~PORT_POWER; 1059 break; 1060 case USB_PORT_FEAT_C_RESET: 1061 case USB_PORT_FEAT_C_CONNECTION: 1062 case USB_PORT_FEAT_C_OVER_CURRENT: 1063 case USB_PORT_FEAT_C_ENABLE: 1064 xhci_clear_port_change_bit((le16_to_cpu(req->value)), 1065 le16_to_cpu(req->index), 1066 status_reg, reg); 1067 break; 1068 default: 1069 printf("unknown feature %x\n", le16_to_cpu(req->value)); 1070 goto unknown; 1071 } 1072 xhci_writel(status_reg, reg); 1073 break; 1074 default: 1075 puts("Unknown request\n"); 1076 goto unknown; 1077 } 1078 1079 debug("scrlen = %d\n req->length = %d\n", 1080 srclen, le16_to_cpu(req->length)); 1081 1082 len = min(srclen, (int)le16_to_cpu(req->length)); 1083 1084 if (srcptr != NULL && len > 0) 1085 memcpy(buffer, srcptr, len); 1086 else 1087 debug("Len is 0\n"); 1088 1089 udev->act_len = len; 1090 udev->status = 0; 1091 1092 return 0; 1093 1094 unknown: 1095 udev->act_len = 0; 1096 udev->status = USB_ST_STALLED; 1097 1098 return -ENODEV; 1099 } 1100 1101 /** 1102 * Submits the INT request to XHCI Host cotroller 1103 * 1104 * @param udev pointer to the USB device 1105 * @param pipe contains the DIR_IN or OUT , devnum 1106 * @param buffer buffer to be read/written based on the request 1107 * @param length length of the buffer 1108 * @param interval interval of the interrupt 1109 * @return 0 1110 */ 1111 static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe, 1112 void *buffer, int length, int interval) 1113 { 1114 if (usb_pipetype(pipe) != PIPE_INTERRUPT) { 1115 printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); 1116 return -EINVAL; 1117 } 1118 1119 /* 1120 * xHCI uses normal TRBs for both bulk and interrupt. When the 1121 * interrupt endpoint is to be serviced, the xHC will consume 1122 * (at most) one TD. A TD (comprised of sg list entries) can 1123 * take several service intervals to transmit. 1124 */ 1125 return xhci_bulk_tx(udev, pipe, length, buffer); 1126 } 1127 1128 /** 1129 * submit the BULK type of request to the USB Device 1130 * 1131 * @param udev pointer to the USB device 1132 * @param pipe contains the DIR_IN or OUT , devnum 1133 * @param buffer buffer to be read/written based on the request 1134 * @param length length of the buffer 1135 * @return returns 0 if successful else -1 on failure 1136 */ 1137 static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe, 1138 void *buffer, int length) 1139 { 1140 if (usb_pipetype(pipe) != PIPE_BULK) { 1141 printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); 1142 return -EINVAL; 1143 } 1144 1145 return xhci_bulk_tx(udev, pipe, length, buffer); 1146 } 1147 1148 /** 1149 * submit the control type of request to the Root hub/Device based on the devnum 1150 * 1151 * @param udev pointer to the USB device 1152 * @param pipe contains the DIR_IN or OUT , devnum 1153 * @param buffer buffer to be read/written based on the request 1154 * @param length length of the buffer 1155 * @param setup Request type 1156 * @param root_portnr Root port number that this device is on 1157 * @return returns 0 if successful else -1 on failure 1158 */ 1159 static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe, 1160 void *buffer, int length, 1161 struct devrequest *setup, int root_portnr) 1162 { 1163 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); 1164 int ret = 0; 1165 1166 if (usb_pipetype(pipe) != PIPE_CONTROL) { 1167 printf("non-control pipe (type=%lu)", usb_pipetype(pipe)); 1168 return -EINVAL; 1169 } 1170 1171 if (usb_pipedevice(pipe) == ctrl->rootdev) 1172 return xhci_submit_root(udev, pipe, buffer, setup); 1173 1174 if (setup->request == USB_REQ_SET_ADDRESS && 1175 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) 1176 return xhci_address_device(udev, root_portnr); 1177 1178 if (setup->request == USB_REQ_SET_CONFIGURATION && 1179 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 1180 ret = xhci_set_configuration(udev); 1181 if (ret) { 1182 puts("Failed to configure xHCI endpoint\n"); 1183 return ret; 1184 } 1185 } 1186 1187 return xhci_ctrl_tx(udev, pipe, setup, length, buffer); 1188 } 1189 1190 static int xhci_lowlevel_init(struct xhci_ctrl *ctrl) 1191 { 1192 struct xhci_hccr *hccr; 1193 struct xhci_hcor *hcor; 1194 uint32_t val; 1195 uint32_t val2; 1196 uint32_t reg; 1197 1198 hccr = ctrl->hccr; 1199 hcor = ctrl->hcor; 1200 /* 1201 * Program the Number of Device Slots Enabled field in the CONFIG 1202 * register with the max value of slots the HC can handle. 1203 */ 1204 val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK); 1205 val2 = xhci_readl(&hcor->or_config); 1206 val |= (val2 & ~HCS_SLOTS_MASK); 1207 xhci_writel(&hcor->or_config, val); 1208 1209 /* initializing xhci data structures */ 1210 if (xhci_mem_init(ctrl, hccr, hcor) < 0) 1211 return -ENOMEM; 1212 1213 reg = xhci_readl(&hccr->cr_hcsparams1); 1214 descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >> 1215 HCS_MAX_PORTS_SHIFT); 1216 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); 1217 1218 /* Port Indicators */ 1219 reg = xhci_readl(&hccr->cr_hccparams); 1220 if (HCS_INDICATOR(reg)) 1221 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 1222 | 0x80, &descriptor.hub.wHubCharacteristics); 1223 1224 /* Port Power Control */ 1225 if (HCC_PPC(reg)) 1226 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics) 1227 | 0x01, &descriptor.hub.wHubCharacteristics); 1228 1229 if (xhci_start(hcor)) { 1230 xhci_reset(hcor); 1231 return -ENODEV; 1232 } 1233 1234 /* Zero'ing IRQ control register and IRQ pending register */ 1235 xhci_writel(&ctrl->ir_set->irq_control, 0x0); 1236 xhci_writel(&ctrl->ir_set->irq_pending, 0x0); 1237 1238 reg = HC_VERSION(xhci_readl(&hccr->cr_capbase)); 1239 printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff); 1240 1241 return 0; 1242 } 1243 1244 static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl) 1245 { 1246 u32 temp; 1247 1248 xhci_reset(ctrl->hcor); 1249 1250 debug("// Disabling event ring interrupts\n"); 1251 temp = xhci_readl(&ctrl->hcor->or_usbsts); 1252 xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT); 1253 temp = xhci_readl(&ctrl->ir_set->irq_pending); 1254 xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp)); 1255 1256 return 0; 1257 } 1258 1259 #ifndef CONFIG_DM_USB 1260 int submit_control_msg(struct usb_device *udev, unsigned long pipe, 1261 void *buffer, int length, struct devrequest *setup) 1262 { 1263 struct usb_device *hop = udev; 1264 1265 if (hop->parent) 1266 while (hop->parent->parent) 1267 hop = hop->parent; 1268 1269 return _xhci_submit_control_msg(udev, pipe, buffer, length, setup, 1270 hop->portnr); 1271 } 1272 1273 int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer, 1274 int length) 1275 { 1276 return _xhci_submit_bulk_msg(udev, pipe, buffer, length); 1277 } 1278 1279 int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer, 1280 int length, int interval) 1281 { 1282 return _xhci_submit_int_msg(udev, pipe, buffer, length, interval); 1283 } 1284 1285 /** 1286 * Intialises the XHCI host controller 1287 * and allocates the necessary data structures 1288 * 1289 * @param index index to the host controller data structure 1290 * @return pointer to the intialised controller 1291 */ 1292 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) 1293 { 1294 struct xhci_hccr *hccr; 1295 struct xhci_hcor *hcor; 1296 struct xhci_ctrl *ctrl; 1297 int ret; 1298 1299 *controller = NULL; 1300 1301 if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0) 1302 return -ENODEV; 1303 1304 if (xhci_reset(hcor) != 0) 1305 return -ENODEV; 1306 1307 ctrl = &xhcic[index]; 1308 1309 ctrl->hccr = hccr; 1310 ctrl->hcor = hcor; 1311 1312 ret = xhci_lowlevel_init(ctrl); 1313 1314 if (ret) { 1315 ctrl->hccr = NULL; 1316 ctrl->hcor = NULL; 1317 } else { 1318 *controller = &xhcic[index]; 1319 } 1320 1321 return ret; 1322 } 1323 1324 /** 1325 * Stops the XHCI host controller 1326 * and cleans up all the related data structures 1327 * 1328 * @param index index to the host controller data structure 1329 * @return none 1330 */ 1331 int usb_lowlevel_stop(int index) 1332 { 1333 struct xhci_ctrl *ctrl = (xhcic + index); 1334 1335 if (ctrl->hcor) { 1336 xhci_lowlevel_stop(ctrl); 1337 xhci_hcd_stop(index); 1338 xhci_cleanup(ctrl); 1339 } 1340 1341 return 0; 1342 } 1343 #endif /* CONFIG_DM_USB */ 1344 1345 #ifdef CONFIG_DM_USB 1346 1347 static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev, 1348 unsigned long pipe, void *buffer, int length, 1349 struct devrequest *setup) 1350 { 1351 struct usb_device *uhop; 1352 struct udevice *hub; 1353 int root_portnr = 0; 1354 1355 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, 1356 dev->name, udev, udev->dev->name, udev->portnr); 1357 hub = udev->dev; 1358 if (device_get_uclass_id(hub) == UCLASS_USB_HUB) { 1359 /* Figure out our port number on the root hub */ 1360 if (usb_hub_is_root_hub(hub)) { 1361 root_portnr = udev->portnr; 1362 } else { 1363 while (!usb_hub_is_root_hub(hub->parent)) 1364 hub = hub->parent; 1365 uhop = dev_get_parent_priv(hub); 1366 root_portnr = uhop->portnr; 1367 } 1368 } 1369 /* 1370 struct usb_device *hop = udev; 1371 1372 if (hop->parent) 1373 while (hop->parent->parent) 1374 hop = hop->parent; 1375 */ 1376 return _xhci_submit_control_msg(udev, pipe, buffer, length, setup, 1377 root_portnr); 1378 } 1379 1380 static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, 1381 unsigned long pipe, void *buffer, int length) 1382 { 1383 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1384 return _xhci_submit_bulk_msg(udev, pipe, buffer, length); 1385 } 1386 1387 static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev, 1388 unsigned long pipe, void *buffer, int length, 1389 int interval) 1390 { 1391 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1392 return _xhci_submit_int_msg(udev, pipe, buffer, length, interval); 1393 } 1394 1395 static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev) 1396 { 1397 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1398 return _xhci_alloc_device(udev); 1399 } 1400 1401 static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev) 1402 { 1403 struct xhci_ctrl *ctrl = dev_get_priv(dev); 1404 struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev); 1405 struct xhci_virt_device *virt_dev; 1406 struct xhci_input_control_ctx *ctrl_ctx; 1407 struct xhci_container_ctx *out_ctx; 1408 struct xhci_container_ctx *in_ctx; 1409 struct xhci_slot_ctx *slot_ctx; 1410 int slot_id = udev->slot_id; 1411 unsigned think_time; 1412 1413 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); 1414 1415 /* Ignore root hubs */ 1416 if (usb_hub_is_root_hub(udev->dev)) 1417 return 0; 1418 1419 virt_dev = ctrl->devs[slot_id]; 1420 BUG_ON(!virt_dev); 1421 1422 out_ctx = virt_dev->out_ctx; 1423 in_ctx = virt_dev->in_ctx; 1424 1425 ctrl_ctx = xhci_get_input_control_ctx(in_ctx); 1426 /* Initialize the input context control */ 1427 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); 1428 ctrl_ctx->drop_flags = 0; 1429 1430 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size); 1431 1432 /* slot context */ 1433 xhci_slot_copy(ctrl, in_ctx, out_ctx); 1434 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx); 1435 1436 /* Update hub related fields */ 1437 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB); 1438 /* 1439 * refer to section 6.2.2: MTT should be 0 for full speed hub, 1440 * but it may be already set to 1 when setup an xHCI virtual 1441 * device, so clear it anyway. 1442 */ 1443 if (hub->tt.multi) 1444 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); 1445 else if (udev->speed == USB_SPEED_FULL) 1446 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT); 1447 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild)); 1448 /* 1449 * Set TT think time - convert from ns to FS bit times. 1450 * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns 1451 * 1452 * 0 = 8 FS bit times, 1 = 16 FS bit times, 1453 * 2 = 24 FS bit times, 3 = 32 FS bit times. 1454 * 1455 * This field shall be 0 if the device is not a high-spped hub. 1456 */ 1457 think_time = hub->tt.think_time; 1458 if (think_time != 0) 1459 think_time = (think_time / 666) - 1; 1460 if (udev->speed == USB_SPEED_HIGH) 1461 slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time)); 1462 slot_ctx->dev_state = 0; 1463 1464 return xhci_configure_endpoints(udev, false); 1465 } 1466 1467 static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size) 1468 { 1469 /* 1470 * xHCD allocates one segment which includes 64 TRBs for each endpoint 1471 * and the last TRB in this segment is configured as a link TRB to form 1472 * a TRB ring. Each TRB can transfer up to 64K bytes, however data 1473 * buffers referenced by transfer TRBs shall not span 64KB boundaries. 1474 * Hence the maximum number of TRBs we can use in one transfer is 62. 1475 */ 1476 *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE; 1477 1478 return 0; 1479 } 1480 1481 int xhci_register(struct udevice *dev, struct xhci_hccr *hccr, 1482 struct xhci_hcor *hcor) 1483 { 1484 struct xhci_ctrl *ctrl = dev_get_priv(dev); 1485 struct usb_bus_priv *priv = dev_get_uclass_priv(dev); 1486 int ret; 1487 1488 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name, 1489 ctrl, hccr, hcor); 1490 1491 ctrl->dev = dev; 1492 1493 /* 1494 * XHCI needs to issue a Address device command to setup 1495 * proper device context structures, before it can interact 1496 * with the device. So a get_descriptor will fail before any 1497 * of that is done for XHCI unlike EHCI. 1498 */ 1499 priv->desc_before_addr = false; 1500 1501 ret = xhci_reset(hcor); 1502 if (ret) 1503 goto err; 1504 1505 ctrl->hccr = hccr; 1506 ctrl->hcor = hcor; 1507 ret = xhci_lowlevel_init(ctrl); 1508 if (ret) 1509 goto err; 1510 1511 return 0; 1512 err: 1513 free(ctrl); 1514 debug("%s: failed, ret=%d\n", __func__, ret); 1515 return ret; 1516 } 1517 1518 int xhci_deregister(struct udevice *dev) 1519 { 1520 struct xhci_ctrl *ctrl = dev_get_priv(dev); 1521 1522 xhci_lowlevel_stop(ctrl); 1523 xhci_cleanup(ctrl); 1524 1525 return 0; 1526 } 1527 1528 struct dm_usb_ops xhci_usb_ops = { 1529 .control = xhci_submit_control_msg, 1530 .bulk = xhci_submit_bulk_msg, 1531 .interrupt = xhci_submit_int_msg, 1532 .alloc_device = xhci_alloc_device, 1533 .update_hub_device = xhci_update_hub_device, 1534 .get_max_xfer_size = xhci_get_max_xfer_size, 1535 }; 1536 1537 #endif 1538
