1 #ifndef A2XX_XML 2 #define A2XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13612 bytes, from 2017-12-19 18:19:46) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 34499 bytes, from 2018-01-03 15:58:51) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2017-12-19 18:19:46) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 146261 bytes, from 2018-01-03 15:58:51) 19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27) 20 21 Copyright (C) 2013-2017 by the following authors: 22 - Rob Clark <robdclark (at) gmail.com> (robclark) 23 - Ilia Mirkin <imirkin (at) alum.mit.edu> (imirkin) 24 25 Permission is hereby granted, free of charge, to any person obtaining 26 a copy of this software and associated documentation files (the 27 "Software"), to deal in the Software without restriction, including 28 without limitation the rights to use, copy, modify, merge, publish, 29 distribute, sublicense, and/or sell copies of the Software, and to 30 permit persons to whom the Software is furnished to do so, subject to 31 the following conditions: 32 33 The above copyright notice and this permission notice (including the 34 next paragraph) shall be included in all copies or substantial 35 portions of the Software. 36 37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46 47 enum a2xx_rb_dither_type { 48 DITHER_PIXEL = 0, 49 DITHER_SUBPIXEL = 1, 50 }; 51 52 enum a2xx_colorformatx { 53 COLORX_4_4_4_4 = 0, 54 COLORX_1_5_5_5 = 1, 55 COLORX_5_6_5 = 2, 56 COLORX_8 = 3, 57 COLORX_8_8 = 4, 58 COLORX_8_8_8_8 = 5, 59 COLORX_S8_8_8_8 = 6, 60 COLORX_16_FLOAT = 7, 61 COLORX_16_16_FLOAT = 8, 62 COLORX_16_16_16_16_FLOAT = 9, 63 COLORX_32_FLOAT = 10, 64 COLORX_32_32_FLOAT = 11, 65 COLORX_32_32_32_32_FLOAT = 12, 66 COLORX_2_3_3 = 13, 67 COLORX_8_8_8 = 14, 68 }; 69 70 enum a2xx_sq_surfaceformat { 71 FMT_1_REVERSE = 0, 72 FMT_1 = 1, 73 FMT_8 = 2, 74 FMT_1_5_5_5 = 3, 75 FMT_5_6_5 = 4, 76 FMT_6_5_5 = 5, 77 FMT_8_8_8_8 = 6, 78 FMT_2_10_10_10 = 7, 79 FMT_8_A = 8, 80 FMT_8_B = 9, 81 FMT_8_8 = 10, 82 FMT_Cr_Y1_Cb_Y0 = 11, 83 FMT_Y1_Cr_Y0_Cb = 12, 84 FMT_5_5_5_1 = 13, 85 FMT_8_8_8_8_A = 14, 86 FMT_4_4_4_4 = 15, 87 FMT_10_11_11 = 16, 88 FMT_11_11_10 = 17, 89 FMT_DXT1 = 18, 90 FMT_DXT2_3 = 19, 91 FMT_DXT4_5 = 20, 92 FMT_24_8 = 22, 93 FMT_24_8_FLOAT = 23, 94 FMT_16 = 24, 95 FMT_16_16 = 25, 96 FMT_16_16_16_16 = 26, 97 FMT_16_EXPAND = 27, 98 FMT_16_16_EXPAND = 28, 99 FMT_16_16_16_16_EXPAND = 29, 100 FMT_16_FLOAT = 30, 101 FMT_16_16_FLOAT = 31, 102 FMT_16_16_16_16_FLOAT = 32, 103 FMT_32 = 33, 104 FMT_32_32 = 34, 105 FMT_32_32_32_32 = 35, 106 FMT_32_FLOAT = 36, 107 FMT_32_32_FLOAT = 37, 108 FMT_32_32_32_32_FLOAT = 38, 109 FMT_32_AS_8 = 39, 110 FMT_32_AS_8_8 = 40, 111 FMT_16_MPEG = 41, 112 FMT_16_16_MPEG = 42, 113 FMT_8_INTERLACED = 43, 114 FMT_32_AS_8_INTERLACED = 44, 115 FMT_32_AS_8_8_INTERLACED = 45, 116 FMT_16_INTERLACED = 46, 117 FMT_16_MPEG_INTERLACED = 47, 118 FMT_16_16_MPEG_INTERLACED = 48, 119 FMT_DXN = 49, 120 FMT_8_8_8_8_AS_16_16_16_16 = 50, 121 FMT_DXT1_AS_16_16_16_16 = 51, 122 FMT_DXT2_3_AS_16_16_16_16 = 52, 123 FMT_DXT4_5_AS_16_16_16_16 = 53, 124 FMT_2_10_10_10_AS_16_16_16_16 = 54, 125 FMT_10_11_11_AS_16_16_16_16 = 55, 126 FMT_11_11_10_AS_16_16_16_16 = 56, 127 FMT_32_32_32_FLOAT = 57, 128 FMT_DXT3A = 58, 129 FMT_DXT5A = 59, 130 FMT_CTX1 = 60, 131 FMT_DXT3A_AS_1_1_1_1 = 61, 132 }; 133 134 enum a2xx_sq_ps_vtx_mode { 135 POSITION_1_VECTOR = 0, 136 POSITION_2_VECTORS_UNUSED = 1, 137 POSITION_2_VECTORS_SPRITE = 2, 138 POSITION_2_VECTORS_EDGE = 3, 139 POSITION_2_VECTORS_KILL = 4, 140 POSITION_2_VECTORS_SPRITE_KILL = 5, 141 POSITION_2_VECTORS_EDGE_KILL = 6, 142 MULTIPASS = 7, 143 }; 144 145 enum a2xx_sq_sample_cntl { 146 CENTROIDS_ONLY = 0, 147 CENTERS_ONLY = 1, 148 CENTROIDS_AND_CENTERS = 2, 149 }; 150 151 enum a2xx_dx_clip_space { 152 DXCLIP_OPENGL = 0, 153 DXCLIP_DIRECTX = 1, 154 }; 155 156 enum a2xx_pa_su_sc_polymode { 157 POLY_DISABLED = 0, 158 POLY_DUALMODE = 1, 159 }; 160 161 enum a2xx_rb_edram_mode { 162 EDRAM_NOP = 0, 163 COLOR_DEPTH = 4, 164 DEPTH_ONLY = 5, 165 EDRAM_COPY = 6, 166 }; 167 168 enum a2xx_pa_sc_pattern_bit_order { 169 LITTLE = 0, 170 BIG = 1, 171 }; 172 173 enum a2xx_pa_sc_auto_reset_cntl { 174 NEVER = 0, 175 EACH_PRIMITIVE = 1, 176 EACH_PACKET = 2, 177 }; 178 179 enum a2xx_pa_pixcenter { 180 PIXCENTER_D3D = 0, 181 PIXCENTER_OGL = 1, 182 }; 183 184 enum a2xx_pa_roundmode { 185 TRUNCATE = 0, 186 ROUND = 1, 187 ROUNDTOEVEN = 2, 188 ROUNDTOODD = 3, 189 }; 190 191 enum a2xx_pa_quantmode { 192 ONE_SIXTEENTH = 0, 193 ONE_EIGTH = 1, 194 ONE_QUARTER = 2, 195 ONE_HALF = 3, 196 ONE = 4, 197 }; 198 199 enum a2xx_rb_copy_sample_select { 200 SAMPLE_0 = 0, 201 SAMPLE_1 = 1, 202 SAMPLE_2 = 2, 203 SAMPLE_3 = 3, 204 SAMPLE_01 = 4, 205 SAMPLE_23 = 5, 206 SAMPLE_0123 = 6, 207 }; 208 209 enum a2xx_rb_blend_opcode { 210 BLEND2_DST_PLUS_SRC = 0, 211 BLEND2_SRC_MINUS_DST = 1, 212 BLEND2_MIN_DST_SRC = 2, 213 BLEND2_MAX_DST_SRC = 3, 214 BLEND2_DST_MINUS_SRC = 4, 215 BLEND2_DST_PLUS_SRC_BIAS = 5, 216 }; 217 218 enum adreno_mmu_clnt_beh { 219 BEH_NEVR = 0, 220 BEH_TRAN_RNG = 1, 221 BEH_TRAN_FLT = 2, 222 }; 223 224 enum sq_tex_clamp { 225 SQ_TEX_WRAP = 0, 226 SQ_TEX_MIRROR = 1, 227 SQ_TEX_CLAMP_LAST_TEXEL = 2, 228 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 229 SQ_TEX_CLAMP_HALF_BORDER = 4, 230 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 231 SQ_TEX_CLAMP_BORDER = 6, 232 SQ_TEX_MIRROR_ONCE_BORDER = 7, 233 }; 234 235 enum sq_tex_swiz { 236 SQ_TEX_X = 0, 237 SQ_TEX_Y = 1, 238 SQ_TEX_Z = 2, 239 SQ_TEX_W = 3, 240 SQ_TEX_ZERO = 4, 241 SQ_TEX_ONE = 5, 242 }; 243 244 enum sq_tex_filter { 245 SQ_TEX_FILTER_POINT = 0, 246 SQ_TEX_FILTER_BILINEAR = 1, 247 SQ_TEX_FILTER_BICUBIC = 2, 248 }; 249 250 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 251 252 #define REG_A2XX_RBBM_CNTL 0x0000003b 253 254 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 255 256 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 257 258 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 259 260 #define REG_A2XX_MH_MMU_CONFIG 0x00000040 261 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 262 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 263 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 264 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 265 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 266 { 267 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 268 } 269 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 270 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 271 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 272 { 273 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 274 } 275 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 276 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 277 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 278 { 279 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 280 } 281 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 282 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 283 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 284 { 285 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 286 } 287 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 288 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 289 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 290 { 291 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 292 } 293 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 294 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 295 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 296 { 297 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 298 } 299 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 300 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 301 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 302 { 303 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 304 } 305 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 306 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 307 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 308 { 309 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 310 } 311 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 312 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 313 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 314 { 315 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 316 } 317 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 318 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 319 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 320 { 321 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 322 } 323 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 324 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 325 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 326 { 327 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 328 } 329 330 #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 331 332 #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 333 334 #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 335 336 #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 337 338 #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 339 340 #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 341 342 #define REG_A2XX_MH_MMU_MPU_END 0x00000047 343 344 #define REG_A2XX_NQWAIT_UNTIL 0x00000394 345 346 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 347 348 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 349 350 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 351 352 #define REG_A2XX_RBBM_DEBUG 0x0000039b 353 354 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 355 #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 356 #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 357 #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 358 #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 359 #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 360 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 361 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 362 #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 363 #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 364 #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 365 #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 366 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 367 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 368 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 369 #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 370 #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 371 #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 372 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 373 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 374 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 375 #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 376 #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 377 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 378 #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 379 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 380 #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 381 #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 382 #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 383 #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 384 #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 385 #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 386 #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 387 388 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 389 390 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 391 392 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 393 394 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 395 396 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 397 398 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 399 400 #define REG_A2XX_RBBM_INT_ACK 0x000003b6 401 402 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 403 404 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 405 406 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 407 408 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 409 410 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 411 412 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 413 414 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 415 416 #define REG_A2XX_RBBM_STATUS 0x000005d0 417 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 418 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 419 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 420 { 421 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 422 } 423 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 424 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 425 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 426 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 427 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 428 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 429 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 430 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 431 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 432 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 433 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 434 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 435 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 436 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 437 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 438 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 439 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 440 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 441 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 442 443 #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 444 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 445 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 446 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 447 { 448 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 449 } 450 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 451 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 452 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 453 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 454 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 455 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 456 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 457 { 458 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 459 } 460 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 461 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 462 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 463 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 464 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 465 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 466 { 467 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 468 } 469 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 470 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 471 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 472 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 473 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 474 475 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 476 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 477 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 478 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 479 { 480 assert(!(val & 0x1f)); 481 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 482 } 483 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 484 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 485 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 486 { 487 assert(!(val & 0x1f)); 488 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 489 } 490 491 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 492 493 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 494 495 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 496 497 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 498 499 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 500 501 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 502 503 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 504 505 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 506 507 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 508 509 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 510 511 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 512 513 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 514 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0 515 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5 516 static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) 517 { 518 return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; 519 } 520 521 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 522 #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001 523 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0 524 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4 525 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) 526 { 527 return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; 528 } 529 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000 530 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12 531 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) 532 { 533 return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; 534 } 535 536 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 537 538 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 539 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff 540 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0 541 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) 542 { 543 return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; 544 } 545 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000 546 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16 547 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) 548 { 549 return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; 550 } 551 552 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 553 554 #define REG_A2XX_SQ_INT_CNTL 0x00000d34 555 556 #define REG_A2XX_SQ_INT_STATUS 0x00000d35 557 558 #define REG_A2XX_SQ_INT_ACK 0x00000d36 559 560 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 561 562 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 563 564 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 565 566 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 567 568 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 569 570 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 571 572 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 573 574 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 575 576 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 577 578 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 579 580 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 581 582 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 583 584 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 585 586 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 587 588 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 589 590 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 591 592 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 593 594 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 595 596 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 597 598 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 599 600 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 601 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 602 603 #define REG_A2XX_TP0_CHICKEN 0x00000e1e 604 605 #define REG_A2XX_RB_BC_CONTROL 0x00000f01 606 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 607 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 608 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 609 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 610 { 611 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 612 } 613 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 614 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 615 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 616 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 617 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 618 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 619 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 620 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 621 { 622 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 623 } 624 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 625 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 626 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 627 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 628 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 629 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 630 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 631 { 632 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 633 } 634 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 635 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 636 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 637 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 638 { 639 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 640 } 641 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 642 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 643 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 644 { 645 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 646 } 647 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 648 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 649 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 650 651 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 652 653 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 654 655 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 656 657 #define REG_A2XX_RB_SURFACE_INFO 0x00002000 658 659 #define REG_A2XX_RB_COLOR_INFO 0x00002001 660 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 661 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 662 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 663 { 664 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 665 } 666 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 667 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 668 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 669 { 670 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 671 } 672 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 673 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 674 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 675 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 676 { 677 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 678 } 679 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 680 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 681 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 682 { 683 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 684 } 685 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 686 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 687 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 688 { 689 assert(!(val & 0x3ff)); 690 return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 691 } 692 693 #define REG_A2XX_RB_DEPTH_INFO 0x00002002 694 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 695 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 696 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 697 { 698 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 699 } 700 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 701 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 702 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 703 { 704 assert(!(val & 0x3ff)); 705 return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 706 } 707 708 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 709 710 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 711 712 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 713 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 714 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 715 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 716 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 717 { 718 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 719 } 720 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 721 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 722 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 723 { 724 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 725 } 726 727 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 728 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 729 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 730 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 731 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 732 { 733 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 734 } 735 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 736 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 737 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 738 { 739 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 740 } 741 742 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 743 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 744 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 745 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 746 { 747 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 748 } 749 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 750 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 751 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 752 { 753 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 754 } 755 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 756 757 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 758 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 759 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 760 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 761 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 762 { 763 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 764 } 765 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 766 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 767 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 768 { 769 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 770 } 771 772 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 773 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 774 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 775 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 776 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 777 { 778 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 779 } 780 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 781 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 782 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 783 { 784 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 785 } 786 787 #define REG_A2XX_UNKNOWN_2010 0x00002010 788 789 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 790 791 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 792 793 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 794 795 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 796 797 #define REG_A2XX_RB_COLOR_MASK 0x00002104 798 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 799 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 800 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 801 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 802 803 #define REG_A2XX_RB_BLEND_RED 0x00002105 804 805 #define REG_A2XX_RB_BLEND_GREEN 0x00002106 806 807 #define REG_A2XX_RB_BLEND_BLUE 0x00002107 808 809 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 810 811 #define REG_A2XX_RB_FOG_COLOR 0x00002109 812 #define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff 813 #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0 814 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) 815 { 816 return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; 817 } 818 #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00 819 #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8 820 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) 821 { 822 return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; 823 } 824 #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000 825 #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16 826 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) 827 { 828 return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; 829 } 830 831 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 832 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 833 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 834 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 835 { 836 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 837 } 838 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 839 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 840 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 841 { 842 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 843 } 844 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 845 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 846 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 847 { 848 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 849 } 850 851 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 852 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 853 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 854 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 855 { 856 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 857 } 858 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 859 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 860 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 861 { 862 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 863 } 864 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 865 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 866 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 867 { 868 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 869 } 870 871 #define REG_A2XX_RB_ALPHA_REF 0x0000210e 872 873 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 874 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 875 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 876 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 877 { 878 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 879 } 880 881 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 882 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 883 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 884 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 885 { 886 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 887 } 888 889 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 890 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 891 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 892 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 893 { 894 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 895 } 896 897 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 898 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 899 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 900 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 901 { 902 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 903 } 904 905 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 906 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 907 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 908 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 909 { 910 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 911 } 912 913 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 914 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 915 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 916 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 917 { 918 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 919 } 920 921 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 922 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 923 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 924 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 925 { 926 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 927 } 928 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 929 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 930 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 931 { 932 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 933 } 934 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 935 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 936 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 937 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 938 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 939 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 940 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 941 { 942 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 943 } 944 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 945 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 946 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 947 { 948 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 949 } 950 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 951 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 952 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 953 { 954 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 955 } 956 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 957 958 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 959 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 960 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 961 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 962 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 963 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 964 { 965 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 966 } 967 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 968 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 969 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 970 { 971 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 972 } 973 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 974 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 975 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 976 977 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 978 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff 979 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0 980 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) 981 { 982 return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; 983 } 984 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000 985 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16 986 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) 987 { 988 return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; 989 } 990 991 #define REG_A2XX_SQ_WRAPPING_0 0x00002183 992 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f 993 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0 994 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) 995 { 996 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; 997 } 998 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0 999 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4 1000 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) 1001 { 1002 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; 1003 } 1004 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00 1005 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8 1006 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) 1007 { 1008 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; 1009 } 1010 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000 1011 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12 1012 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) 1013 { 1014 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; 1015 } 1016 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000 1017 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16 1018 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) 1019 { 1020 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; 1021 } 1022 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000 1023 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20 1024 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) 1025 { 1026 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; 1027 } 1028 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000 1029 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24 1030 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) 1031 { 1032 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; 1033 } 1034 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000 1035 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28 1036 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) 1037 { 1038 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; 1039 } 1040 1041 #define REG_A2XX_SQ_WRAPPING_1 0x00002184 1042 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f 1043 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0 1044 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) 1045 { 1046 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; 1047 } 1048 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0 1049 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4 1050 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) 1051 { 1052 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; 1053 } 1054 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00 1055 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8 1056 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) 1057 { 1058 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; 1059 } 1060 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000 1061 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12 1062 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) 1063 { 1064 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; 1065 } 1066 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000 1067 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16 1068 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) 1069 { 1070 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; 1071 } 1072 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000 1073 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20 1074 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) 1075 { 1076 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; 1077 } 1078 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000 1079 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24 1080 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) 1081 { 1082 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; 1083 } 1084 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000 1085 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28 1086 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) 1087 { 1088 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; 1089 } 1090 1091 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 1092 #define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff 1093 #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0 1094 static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) 1095 { 1096 return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; 1097 } 1098 #define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000 1099 #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12 1100 static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) 1101 { 1102 return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; 1103 } 1104 1105 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 1106 #define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff 1107 #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0 1108 static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) 1109 { 1110 return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; 1111 } 1112 #define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000 1113 #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12 1114 static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) 1115 { 1116 return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; 1117 } 1118 1119 #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 1120 1121 #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 1122 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 1123 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 1124 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 1125 { 1126 return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 1127 } 1128 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 1129 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 1130 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 1131 { 1132 return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 1133 } 1134 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 1135 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 1136 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 1137 { 1138 return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 1139 } 1140 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 1141 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 1142 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 1143 { 1144 return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 1145 } 1146 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 1147 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 1148 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 1149 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 1150 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 1151 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 1152 { 1153 return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 1154 } 1155 1156 #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 1157 1158 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 1159 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 1160 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 1161 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 1162 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 1163 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 1164 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 1165 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 1166 { 1167 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 1168 } 1169 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 1170 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 1171 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 1172 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 1173 { 1174 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 1175 } 1176 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 1177 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 1178 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 1179 { 1180 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 1181 } 1182 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 1183 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 1184 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 1185 { 1186 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 1187 } 1188 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 1189 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 1190 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 1191 { 1192 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 1193 } 1194 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 1195 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 1196 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 1197 { 1198 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 1199 } 1200 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 1201 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 1202 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 1203 { 1204 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 1205 } 1206 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 1207 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 1208 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 1209 { 1210 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 1211 } 1212 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 1213 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 1214 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 1215 { 1216 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 1217 } 1218 1219 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 1220 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 1221 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 1222 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 1223 { 1224 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 1225 } 1226 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 1227 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 1228 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 1229 { 1230 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 1231 } 1232 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 1233 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 1234 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 1235 { 1236 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 1237 } 1238 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 1239 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 1240 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 1241 { 1242 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 1243 } 1244 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 1245 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 1246 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 1247 { 1248 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 1249 } 1250 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 1251 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 1252 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 1253 { 1254 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 1255 } 1256 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 1257 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 1258 1259 #define REG_A2XX_RB_COLORCONTROL 0x00002202 1260 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 1261 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 1262 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 1263 { 1264 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 1265 } 1266 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 1267 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 1268 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 1269 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 1270 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 1271 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 1272 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 1273 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 1274 { 1275 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 1276 } 1277 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 1278 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 1279 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1280 { 1281 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 1282 } 1283 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 1284 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 1285 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 1286 { 1287 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 1288 } 1289 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 1290 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 1291 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 1292 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 1293 { 1294 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 1295 } 1296 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 1297 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 1298 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 1299 { 1300 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 1301 } 1302 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 1303 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 1304 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 1305 { 1306 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 1307 } 1308 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 1309 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 1310 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 1311 { 1312 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 1313 } 1314 1315 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 1316 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 1317 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 1318 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 1319 { 1320 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 1321 } 1322 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 1323 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 1324 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 1325 { 1326 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 1327 } 1328 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 1329 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 1330 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 1331 { 1332 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 1333 } 1334 1335 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 1336 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 1337 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 1338 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 1339 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 1340 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 1341 { 1342 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 1343 } 1344 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 1345 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 1346 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1347 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1348 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1349 1350 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1351 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1352 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1353 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1354 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1355 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1356 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1357 { 1358 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1359 } 1360 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1361 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1362 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1363 { 1364 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1365 } 1366 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1367 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1368 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1369 { 1370 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1371 } 1372 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1373 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1374 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1375 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1376 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1377 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1378 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1379 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1380 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1381 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1382 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1383 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1384 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1385 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1386 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1387 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1388 1389 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1390 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1391 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1392 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1393 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1394 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1395 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1396 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1397 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1398 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1399 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1400 1401 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1402 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1403 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1404 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1405 { 1406 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1407 } 1408 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1409 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1410 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1411 { 1412 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1413 } 1414 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1415 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1416 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1417 { 1418 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1419 } 1420 1421 #define REG_A2XX_RB_MODECONTROL 0x00002208 1422 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1423 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1424 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1425 { 1426 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1427 } 1428 1429 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1430 1431 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1432 1433 #define REG_A2XX_CLEAR_COLOR 0x0000220b 1434 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1435 #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1436 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1437 { 1438 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1439 } 1440 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1441 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1442 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1443 { 1444 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1445 } 1446 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1447 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1448 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1449 { 1450 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1451 } 1452 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1453 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1454 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1455 { 1456 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1457 } 1458 1459 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1460 1461 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1462 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1463 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1464 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1465 { 1466 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1467 } 1468 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1469 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1470 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1471 { 1472 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1473 } 1474 1475 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1476 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1477 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1478 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1479 { 1480 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1481 } 1482 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1483 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1484 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1485 { 1486 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1487 } 1488 1489 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1490 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1491 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1492 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1493 { 1494 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1495 } 1496 1497 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1498 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1499 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1500 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1501 { 1502 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1503 } 1504 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1505 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1506 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1507 { 1508 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1509 } 1510 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1511 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1512 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1513 { 1514 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1515 } 1516 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1517 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1518 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1519 { 1520 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1521 } 1522 1523 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1524 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001 1525 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e 1526 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1 1527 static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) 1528 { 1529 return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; 1530 } 1531 #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100 1532 1533 #define REG_A2XX_VGT_ENHANCE 0x00002294 1534 1535 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1536 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1537 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1538 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1539 { 1540 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1541 } 1542 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1543 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1544 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1545 1546 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1547 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007 1548 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0 1549 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) 1550 { 1551 return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; 1552 } 1553 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000 1554 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13 1555 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) 1556 { 1557 return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; 1558 } 1559 1560 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1561 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1562 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1563 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1564 { 1565 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1566 } 1567 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1568 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1569 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1570 { 1571 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1572 } 1573 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1574 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1575 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1576 { 1577 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1578 } 1579 1580 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1581 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1582 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1583 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1584 { 1585 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1586 } 1587 1588 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1589 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1590 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1591 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1592 { 1593 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1594 } 1595 1596 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1597 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1598 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1599 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1600 { 1601 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1602 } 1603 1604 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1605 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1606 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1607 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1608 { 1609 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1610 } 1611 1612 #define REG_A2XX_SQ_VS_CONST 0x00002307 1613 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1614 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1615 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1616 { 1617 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1618 } 1619 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1620 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1621 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1622 { 1623 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1624 } 1625 1626 #define REG_A2XX_SQ_PS_CONST 0x00002308 1627 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1628 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1629 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1630 { 1631 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1632 } 1633 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1634 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1635 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1636 { 1637 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1638 } 1639 1640 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1641 1642 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1643 1644 #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1645 1646 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1647 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007 1648 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0 1649 static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) 1650 { 1651 return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; 1652 } 1653 1654 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1655 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003 1656 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0 1657 static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) 1658 { 1659 return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; 1660 } 1661 1662 #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1663 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1664 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1665 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1666 { 1667 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1668 } 1669 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1670 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1671 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1672 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1673 { 1674 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1675 } 1676 1677 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1678 1679 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1680 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1681 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1682 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1683 { 1684 assert(!(val & 0x1f)); 1685 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1686 } 1687 1688 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1689 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1690 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1691 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1692 { 1693 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1694 } 1695 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1696 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1697 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1698 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1699 { 1700 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1701 } 1702 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1703 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1704 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1705 { 1706 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1707 } 1708 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1709 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1710 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1711 { 1712 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1713 } 1714 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1715 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1716 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1717 { 1718 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1719 } 1720 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1721 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1722 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1723 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1724 1725 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1726 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1727 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1728 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1729 { 1730 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1731 } 1732 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1733 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1734 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1735 { 1736 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1737 } 1738 1739 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1740 1741 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1742 1743 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1744 1745 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1746 1747 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1748 1749 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1750 1751 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1752 1753 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1754 1755 #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1756 1757 #define REG_A2XX_SQ_FETCH_0 0x00004800 1758 1759 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1760 1761 #define REG_A2XX_SQ_CF_LOOP 0x00004908 1762 1763 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1764 1765 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1766 1767 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1768 1769 #define REG_A2XX_SQ_TEX_0 0x00000000 1770 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1771 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1772 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1773 { 1774 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1775 } 1776 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1777 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1778 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1779 { 1780 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1781 } 1782 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1783 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1784 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1785 { 1786 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1787 } 1788 #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 1789 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1790 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1791 { 1792 assert(!(val & 0x1f)); 1793 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1794 } 1795 1796 #define REG_A2XX_SQ_TEX_1 0x00000001 1797 1798 #define REG_A2XX_SQ_TEX_2 0x00000002 1799 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1800 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1801 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1802 { 1803 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1804 } 1805 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1806 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1807 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1808 { 1809 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1810 } 1811 1812 #define REG_A2XX_SQ_TEX_3 0x00000003 1813 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1814 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1815 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1816 { 1817 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1818 } 1819 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1820 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1821 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1822 { 1823 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1824 } 1825 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1826 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1827 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1828 { 1829 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1830 } 1831 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1832 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1833 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1834 { 1835 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 1836 } 1837 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 1838 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 1839 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 1840 { 1841 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 1842 } 1843 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 1844 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 1845 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 1846 { 1847 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 1848 } 1849 1850 1851 #endif /* A2XX_XML */ 1852
