| /external/llvm/lib/Target/AVR/MCTargetDesc/ |
| AVRELFStreamer.cpp | 14 if (Features[AVR::ELFArchAVR1])
16 else if (Features[AVR::ELFArchAVR2])
18 else if (Features[AVR::ELFArchAVR25])
20 else if (Features[AVR::ELFArchAVR3])
22 else if (Features[AVR::ELFArchAVR31])
24 else if (Features[AVR::ELFArchAVR35])
26 else if (Features[AVR::ELFArchAVR4])
28 else if (Features[AVR::ELFArchAVR5])
30 else if (Features[AVR::ELFArchAVR51])
32 else if (Features[AVR::ELFArchAVR6]
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/MCTargetDesc/ |
| AVRELFStreamer.cpp | 16 if (Features[AVR::ELFArchAVR1])
18 else if (Features[AVR::ELFArchAVR2])
20 else if (Features[AVR::ELFArchAVR25])
22 else if (Features[AVR::ELFArchAVR3])
24 else if (Features[AVR::ELFArchAVR31])
26 else if (Features[AVR::ELFArchAVR35])
28 else if (Features[AVR::ELFArchAVR4])
30 else if (Features[AVR::ELFArchAVR5])
32 else if (Features[AVR::ELFArchAVR51])
34 else if (Features[AVR::ELFArchAVR6]
[all...] |
| AVRELFObjectWriter.cpp | 1 //===-- AVRELFObjectWriter.cpp - AVR ELF Writer ---------------------------===//
23 /// Writes AVR machine code into an ELF32 object file.
80 case AVR::fixup_32:
82 case AVR::fixup_7_pcrel:
84 case AVR::fixup_13_pcrel:
86 case AVR::fixup_16:
88 case AVR::fixup_16_pm:
90 case AVR::fixup_lo8_ldi:
92 case AVR::fixup_hi8_ldi:
94 case AVR::fixup_hh8_ldi
[all...] |
| AVRMCExpr.cpp | 1 //===-- AVRMCExpr.cpp - AVR specific MC expression classes ----------------===//
145 AVR::Fixups AVRMCExpr::getFixupKind() const {
146 AVR::Fixups Kind = AVR::Fixups::LastTargetFixupKind;
150 Kind = isNegated() ? AVR::fixup_lo8_ldi_neg : AVR::fixup_lo8_ldi;
153 Kind = isNegated() ? AVR::fixup_hi8_ldi_neg : AVR::fixup_hi8_ldi;
156 Kind = isNegated() ? AVR::fixup_hh8_ldi_neg : AVR::fixup_hh8_ldi
[all...] |
| AVRAsmBackend.cpp | 1 //===-- AVRAsmBackend.cpp - AVR Asm Backend ------------------------------===//
83 AVR::fixups::adjustBranchTarget(Value);
96 AVR::fixups::adjustBranchTarget(Value);
255 case AVR::fixup_7_pcrel:
258 case AVR::fixup_13_pcrel:
261 case AVR::fixup_call:
264 case AVR::fixup_ldi:
267 case AVR::fixup_lo8_ldi:
270 case AVR::fixup_lo8_ldi_pm:
271 case AVR::fixup_lo8_ldi_gs
[all...] |
| AVRMCCodeEmitter.cpp | 1 //===-- AVRMCCodeEmitter.cpp - Convert AVR Code to Machine Code -----------===//
77 bool IsRegX = MI.getOperand(0).getReg() == AVR::R27R26 ||
78 MI.getOperand(1).getReg() == AVR::R27R26;
80 bool IsPredec = Opcode == AVR::LDRdPtrPd || Opcode == AVR::STPtrPdRr;
81 bool IsPostinc = Opcode == AVR::LDRdPtrPi || Opcode == AVR::STPtrPiRr;
91 template <AVR::Fixups Fixup>
109 AVR::fixups::adjustBranchTarget(target);
122 case AVR::R27R26: return 0x03; // X: 0b1
[all...] |
| AVRFixupKinds.h | 1 //===-- AVRFixupKinds.h - AVR Specific Fixup Entries ------------*- C++ -*-===//
16 namespace AVR {
25 /// MCFixupKindInfo Infos[AVR::NumTargetFixupKinds]
28 /// A 32-bit AVR fixup.
38 /// The nonmenclature is that AVR branch targets are
137 /// All branch targets in AVR are rightshifted by 1 to take advantage
146 } // end of namespace llvm::AVR
|
| AVRMCCodeEmitter.h | 1 //===-- AVRMCCodeEmitter.h - Convert AVR Code to Machine Code -------------===//
37 /// Writes AVR machine code to a stream.
51 template <AVR::Fixups Fixup>
73 template <AVR::Fixups Fixup, unsigned Offset>
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.cpp | 1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
10 // This file contains the AVR implementation of the TargetRegisterInfo class.
23 #include "AVR.h"
57 Reserved.set(AVR::R0);
58 Reserved.set(AVR::R1);
59 Reserved.set(AVR::R1R0);
62 Reserved.set(AVR::SPL);
63 Reserved.set(AVR::SPH);
64 Reserved.set(AVR::SP);
75 Reserved.set(AVR::R28)
[all...] |
| AVRFrameLowering.cpp | 1 //===-- AVRFrameLowering.cpp - AVR Frame Information ----------------------===//
10 // This file contains the AVR implementation of TargetFrameLowering class.
16 #include "AVR.h"
64 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
72 .addReg(AVR::R29R28, RegState::Kill)
80 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
81 .addReg(AVR::R1R0, RegState::Kill)
84 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0
[all...] |
| AVRInstrInfo.cpp | 1 //===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===//
10 // This file contains the AVR implementation of the TargetInstrInfo class.
28 #include "AVR.h"
40 : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
50 // Not all AVR devices support the 16-bit `MOVW` instruction.
51 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
53 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
62 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
64 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi
[all...] |
| AVRExpandPseudoInsts.cpp | 16 #include "AVR.h"
29 #define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
34 /// actual AVR instructions.
55 const unsigned SCRATCH_REGISTER = AVR::R0;
210 if (Op == AVR::ANDIRdK && ImmVal == 0xff)
214 if (Op == AVR::ORIRdK && ImmVal == 0x0)
258 bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
259 return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI);
263 bool AVRExpandPseudo::expand<AVR::ADCWRdRr>(Block &MBB, BlockIt MBBI)
[all...] |
| AVRISelLowering.cpp | 1 //===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
10 // This file defines the interfaces that AVR uses to lower LLVM code into a
27 #include "AVR.h"
37 addRegisterClass(MVT::i8, &AVR::GPR8RegClass);
38 addRegisterClass(MVT::i16, &AVR::DREGSRegClass);
46 setStackPointerRegisterToSaveRestore(AVR::SP);
158 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
266 assert(!VT.isVector() && "No AVR SetCC type for vectors!");
413 /// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
433 /// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code fo
[all...] |
| AVRRelaxMemOperations.cpp | 15 #include "AVR.h"
27 #define AVR_RELAX_MEM_OPS_NAME "AVR memory operation relaxation pass"
89 bool AVRRelaxMem::relax<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
100 buildMI(MBB, MBBI, AVR::PUSHWRr)
104 buildMI(MBB, MBBI, AVR::SBCIWRdK)
111 buildMI(MBB, MBBI, AVR::STWPtrRr)
116 buildMI(MBB, MBBI, AVR::POPWRd)
134 RELAX(AVR::STDWPtrQRr);
142 INITIALIZE_PASS(AVRRelaxMem, "avr-relax-mem",
|
| AVRTargetObjectFile.cpp | 1 //===-- AVRTargetObjectFile.cpp - AVR Object Files ------------------------===//
19 #include "AVR.h"
34 if (AVR::isProgramMemoryAddress(GO) && !GO->hasSection())
|
| AVRISelDAGToDAG.cpp | 1 //===-- AVRISelDAGToDAG.cpp - A dag to dag inst selector for AVR ----------===//
10 // This file defines an instruction selector for the AVR target.
14 #include "AVR.h"
23 #define DEBUG_TYPE "avr-isel"
27 /// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form).
34 return "AVR DAG->DAG Instruction Selection";
145 Opcode = (isPre) ? AVR::LDRdPtrPd : AVR::LDRdPtrPi;
153 Opcode = (isPre) ? AVR::LDWRdPtrPd : AVR::LDWRdPtrPi
[all...] |
| AVR.h | 1 //===-- AVR.h - Top-level interface for AVR representation ------*- C++ -*-===//
11 // AVR back-end.
37 /// Contains the AVR backend.
38 namespace AVR {
40 /// An integer that identifies all of the supported AVR address spaces.
54 } // end of namespace AVR
|
| AVRAsmPrinter.cpp | 1 //===-- AVRAsmPrinter.cpp - AVR LLVM assembly writer ----------------------===//
11 // of machine-dependent LLVM code to GAS-format AVR assembly language.
15 #include "AVR.h"
33 #define DEBUG_TYPE "avr-asm-printer"
37 /// An AVR assembly code printer.
44 StringRef getPassName() const override { return "AVR Assembly Printer"; }
125 Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi
126 : AVR::sub_lo);
156 if (MI->getOperand(OpNum).getReg() == AVR::R31R30) {
159 assert(MI->getOperand(OpNum).getReg() == AVR::R29R28 &
[all...] |
| /external/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.cpp | 1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
10 // This file contains the AVR implementation of the TargetRegisterInfo class.
23 #include "AVR.h"
59 Reserved.set(AVR::R0);
60 Reserved.set(AVR::R1);
61 Reserved.set(AVR::R1R0);
64 Reserved.set(AVR::SPL);
65 Reserved.set(AVR::SPH);
66 Reserved.set(AVR::SP);
70 Reserved.set(AVR::R28)
[all...] |
| AVRInstrInfo.cpp | 1 //===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===//
10 // This file contains the AVR implementation of the TargetInstrInfo class.
28 #include "AVR.h"
39 : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
47 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) {
48 Opc = AVR::MOVRdRr;
49 } else if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
50 Opc = AVR::MOVWRdRr;
51 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg))
[all...] |
| AVRTargetObjectFile.cpp | 1 //===-- AVRTargetObjectFile.cpp - AVR Object Files ------------------------===//
19 #include "AVR.h"
34 if (AVR::isProgramMemoryAddress(GV) && !GV->hasSection())
|
| AVR.h | 1 //===-- AVR.h - Top-level interface for AVR representation ------*- C++ -*-===//
11 // AVR back-end.
33 /// Contains the AVR backend.
34 namespace AVR {
48 } // end of namespace AVR
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/InstPrinter/ |
| AVRInstPrinter.cpp | 1 //===-- AVRInstPrinter.cpp - Convert AVR MCInst to assembly syntax --------===//
10 // This class prints an AVR MCInst to a .s file.
44 case AVR::LDRdPtr:
45 case AVR::LDRdPtrPi:
46 case AVR::LDRdPtrPd:
51 if (Opcode == AVR::LDRdPtrPd)
56 if (Opcode == AVR::LDRdPtrPi)
59 case AVR::STPtrRr:
65 case AVR::STPtrPiRr:
66 case AVR::STPtrPdRr
[all...] |
| AVRInstPrinter.h | 1 //===- AVRInstPrinter.h - Convert AVR MCInst to assembly syntax -*- C++ -*-===//
10 // This class prints an AVR MCInst to a .s file.
23 /// Prints AVR instructions to a textual stream.
38 unsigned AltIdx = AVR::NoRegAltName);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/AsmParser/ |
| AVRAsmParser.cpp | 1 //===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
10 #include "AVR.h"
35 #define DEBUG_TYPE "avr-asm-parser"
39 /// Parses AVR assembly from a stream.
75 unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
76 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
101 /// An parsed AVR assembly operand.
320 // GCC supports case insensitive register names. Some of the AVR registers
324 if (RegNum == AVR::NoRegister) {
327 if (RegNum == AVR::NoRegister)
[all...] |
