/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
ISDOpcodes.h | 52 // AssertSext, AssertZext - These nodes record if a register contains a 57 AssertSext, AssertZext, [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 52 /// AssertSext, AssertZext - These nodes record if a register contains a 57 AssertSext, AssertZext, [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 52 /// AssertSext, AssertZext - These nodes record if a register contains a 57 AssertSext, AssertZext, [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
Nios2ISelLowering.cpp | 125 Opcode = ISD::AssertSext;
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
BlackfinISelLowering.cpp | 199 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 402 Val = DAG.getNode(ISD::AssertSext, dl, RV.getLocVT(), Val,
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 354 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, 537 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 175 return DAG.getNode(ISD::AssertSext, SDLoc(N), 436 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, [all...] |
SelectionDAGDumper.cpp | 85 case ISD::AssertSext: return "AssertSext";
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 52 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 155 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 369 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, [all...] |
SelectionDAGBuilder.cpp | 96 /// (ISD::AssertSext). 216 /// (ISD::AssertSext). 689 // now, just use the tightest assertzext/assertsext possible. 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, [all...] |
/external/llvm/lib/Target/BPF/ |
BPFISelLowering.cpp | 190 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGDumper.cpp | 106 case ISD::AssertSext: return "AssertSext"; [all...] |
LegalizeIntegerTypes.cpp | 57 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 181 return DAG.getNode(ISD::AssertSext, SDLoc(N), 430 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, [all...] |
LegalizeVectorOps.cpp | 551 : ISD::AssertSext, [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
BPFISelLowering.cpp | 247 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
MBlazeISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 455 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 620 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | 454 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 613 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/Target/Lanai/ |
LanaiISelLowering.cpp | 455 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 455 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
AlphaISelLowering.cpp | 374 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 346 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
SparcISelLowering.cpp | 218 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
LanaiISelLowering.cpp | 471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, [all...] |