/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/ |
fetch_jit.cpp | 166 pVtxOut = BITCAST(pVtxOut, PointerType::get(VectorType::get(mFP32Ty, mVWidth16), 0)); 168 pVtxOut = BITCAST(pVtxOut, PointerType::get(VectorType::get(mFP32Ty, mVWidth), 0)); 171 pVtxOut = BITCAST(pVtxOut, PointerType::get(VectorType::get(mFP32Ty, mVWidth), 0)); 195 indices = BITCAST(indices, Type::getInt8PtrTy(JM()->mContext, 0)); 201 vIndices = LOAD(BITCAST(indices, PointerType::get(VectorType::get(mInt8Ty, mpJitMgr->mVWidth), 0)), {(uint32_t)0}); 204 vIndices2 = LOAD(BITCAST(indices2, PointerType::get(VectorType::get(mInt8Ty, mpJitMgr->mVWidth), 0)), { (uint32_t)0 }); 210 pLastIndex = BITCAST(pLastIndex, Type::getInt8PtrTy(JM()->mContext, 0)); 213 pLastIndex = BITCAST(pLastIndex, Type::getInt8PtrTy(JM()->mContext, 0)); 219 indices = BITCAST(indices, Type::getInt16PtrTy(JM()->mContext, 0)); 225 vIndices = LOAD(BITCAST(indices, PointerType::get(VectorType::get(mInt16Ty, mpJitMgr->mVWidth), 0)), {(uint32_t)0}) [all...] |
builder_misc.cpp | 439 mask = BITCAST(mask,VectorType::get(mInt32Ty,mVWidth)); 441 mask = BITCAST(mask,VectorType::get(mFP32Ty,mVWidth)); 444 vResult = BITCAST(CALL(func,{src,mask}), VectorType::get(mInt32Ty,mVWidth)); 600 Value *mask = BITCAST(VMASK(vMask), mSimdFP32Ty); 621 loadAddress = BITCAST(loadAddress,PointerType::get(mFP32Ty,0)); 645 Value *mask = BITCAST(vMask, mInt16Ty); 703 loadAddress = BITCAST(loadAddress, PointerType::get(mInt32Ty, 0)); 727 Value *mask = BITCAST(vMask, mInt16Ty); 766 vMask = BITCAST(S_EXT(vMask, VectorType::get(mInt64Ty, mVWidth/2)), VectorType::get(mDoubleTy, mVWidth/2)); 786 loadAddress = BITCAST(loadAddress,PointerType::get(mDoubleTy,0)) [all...] |
streamout_jit.cpp | 147 pAttrib = BITCAST(pAttrib, simd4PtrTy); 155 Value* pOut = BITCAST(pOutBuffers[decl.bufferIndex], PointerType::get(mInt8Ty, 0)); 158 Value* src = BITCAST(vpackedAttrib, simd4Ty); 162 mask = BITCAST(mask, VectorType::get(IRB()->getInt32Ty(), 4));
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blend_jit.cpp | 199 src[c] = BITCAST(VIMMED1((int)info.defaults[c]), mSimdFP32Ty); 212 src[info.swizzle[c]] = BITCAST(VIMMED1((int)info.defaults[info.swizzle[c]]), mSimdFP32Ty); 479 pRef = BITCAST(pRef, mSimdFP32Ty); 698 src[i] = BITCAST(src[i], mSimdInt32Ty); 699 dst[i] = BITCAST(dst[i], mSimdInt32Ty); 745 result[i] = BITCAST(result[i], mSimdFP32Ty);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeTypesGeneric.cpp | 54 llvm_unreachable("Bitcast of a promotion-needing float should never need" 63 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 64 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 75 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 76 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 89 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 90 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 93 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); [all...] |
LegalizeVectorOps.cpp | 418 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); 429 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 466 // PromoteVector which uses bitcast to promote thus assumning that the 751 // Bitcast the operands to be the same type as the mask. 754 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); 755 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 764 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); 808 ISD::BITCAST, DL, VT, 835 // and a bitcast to the wider element type. 859 return DAG.getNode(ISD::BITCAST, DL, VT [all...] |
LegalizeVectorTypes.cpp | 52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 168 return DAG.getNode(ISD::BITCAST, SDLoc(N), 433 case ISD::BITCAST: 483 return DAG.getNode(ISD::BITCAST, SDLoc(N), 594 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 767 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 768 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 776 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 777 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 791 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeTypesGeneric.cpp | 54 llvm_unreachable("Bitcast of a promotion-needing float should never need" 63 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 64 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 75 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 76 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 89 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 90 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 93 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); [all...] |
LegalizeVectorOps.cpp | 490 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); 501 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 529 // PromoteVector which uses bitcast to promote thus assumning that the 800 // Bitcast the operands to be the same type as the mask. 803 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); 804 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 813 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); 857 ISD::BITCAST, DL, VT, 884 // and a bitcast to the wider element type. [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeTypesGeneric.cpp | 57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 64 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 65 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 71 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 72 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); 78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); 81 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); 91 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo) [all...] |
LegalizeVectorOps.cpp | 255 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); 262 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 284 // Bitcast the operands to be the same type as the mask. 287 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); 288 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
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LegalizeVectorTypes.cpp | 51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 313 case ISD::BITCAST: 347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 423 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; 542 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 543 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 551 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); 552 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); 566 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo) [all...] |
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
X86GenDAGISel.inc | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/ |
Nios2ISelLowering.cpp | 55 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); 137 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 351 setOperationAction(ISD::BITCAST, MVT::i32, Legal); 352 setOperationAction(ISD::BITCAST, MVT::f32, Legal); 353 setOperationAction(ISD::BITCAST, MVT::i64, Legal); 354 setOperationAction(ISD::BITCAST, MVT::f64, Legal); 678 DAG.getNode(ISD::BITCAST, dl, vecVT, result)); 691 ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones); 717 result = DAG.getNode(ISD::BITCAST, dl, vecVT, [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
ISDOpcodes.h | 418 // BITCAST - This operator converts between integer, vector and FP 425 BITCAST, [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SIISelLowering.cpp | 249 case ISD::BITCAST: 483 case ISD::BITCAST: [all...] |
AMDGPUISelLowering.cpp | 520 setTargetDAGCombine(ISD::BITCAST); 596 // TODO: Should really be looking at the users of the bitcast. These are 599 case ISD::BITCAST: [all...] |
/external/llvm/lib/Target/AMDGPU/ |
AMDGPUISelLowering.cpp | 474 setTargetDAGCombine(ISD::BITCAST); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
SparcISelLowering.cpp | 208 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 216 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 263 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 430 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 520 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 728 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 729 setOperationAction(ISD::BITCAST, MVT::i32, Expand); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
X86ISelLowering.cpp | 332 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 333 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 335 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 337 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelDAGToDAG.cpp | 528 // This function looks through ISD::BITCAST nodes. 529 // TODO: This might not be appropriate for big-endian MSA since BITCAST is 542 if (N->getOpcode() == ISD::BITCAST) 611 // This function looks through ISD::BITCAST nodes. 612 // TODO: This might not be appropriate for big-endian MSA since BITCAST is 618 if (N->getOpcode() == ISD::BITCAST) 642 // This function looks through ISD::BITCAST nodes. 643 // TODO: This might not be appropriate for big-endian MSA since BITCAST is 649 if (N->getOpcode() == ISD::BITCAST) 676 // This function looks through ISD::BITCAST nodes [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | 520 setOperationAction(ISD::BITCAST, MVT::i16, Custom); 521 setOperationAction(ISD::BITCAST, MVT::i32, Custom); 522 setOperationAction(ISD::BITCAST, MVT::f16, Custom); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 385 setOperationAction(ISD::BITCAST, MVT::f32, Legal); 386 setOperationAction(ISD::BITCAST, MVT::i32, Legal); 387 setOperationAction(ISD::BITCAST, MVT::i64, Legal); 388 setOperationAction(ISD::BITCAST, MVT::f64, Legal); 390 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 391 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 392 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 393 setOperationAction(ISD::BITCAST, MVT::f64, Expand); [all...] |