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      1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MipsSEISelDAGToDAG.h"
     15 #include "MCTargetDesc/MipsBaseInfo.h"
     16 #include "Mips.h"
     17 #include "MipsAnalyzeImmediate.h"
     18 #include "MipsMachineFunction.h"
     19 #include "MipsRegisterInfo.h"
     20 #include "llvm/CodeGen/MachineConstantPool.h"
     21 #include "llvm/CodeGen/MachineFrameInfo.h"
     22 #include "llvm/CodeGen/MachineFunction.h"
     23 #include "llvm/CodeGen/MachineInstrBuilder.h"
     24 #include "llvm/CodeGen/MachineRegisterInfo.h"
     25 #include "llvm/CodeGen/SelectionDAGNodes.h"
     26 #include "llvm/IR/CFG.h"
     27 #include "llvm/IR/GlobalValue.h"
     28 #include "llvm/IR/Instructions.h"
     29 #include "llvm/IR/Intrinsics.h"
     30 #include "llvm/IR/Type.h"
     31 #include "llvm/Support/Debug.h"
     32 #include "llvm/Support/ErrorHandling.h"
     33 #include "llvm/Support/raw_ostream.h"
     34 #include "llvm/Target/TargetMachine.h"
     35 using namespace llvm;
     36 
     37 #define DEBUG_TYPE "mips-isel"
     38 
     39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
     40   Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
     41   if (Subtarget->inMips16Mode())
     42     return false;
     43   return MipsDAGToDAGISel::runOnMachineFunction(MF);
     44 }
     45 
     46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
     47                                                MachineFunction &MF) {
     48   MachineInstrBuilder MIB(MF, &MI);
     49   unsigned Mask = MI.getOperand(1).getImm();
     50   unsigned Flag =
     51       IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
     52 
     53   if (Mask & 1)
     54     MIB.addReg(Mips::DSPPos, Flag);
     55 
     56   if (Mask & 2)
     57     MIB.addReg(Mips::DSPSCount, Flag);
     58 
     59   if (Mask & 4)
     60     MIB.addReg(Mips::DSPCarry, Flag);
     61 
     62   if (Mask & 8)
     63     MIB.addReg(Mips::DSPOutFlag, Flag);
     64 
     65   if (Mask & 16)
     66     MIB.addReg(Mips::DSPCCond, Flag);
     67 
     68   if (Mask & 32)
     69     MIB.addReg(Mips::DSPEFI, Flag);
     70 }
     71 
     72 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
     73   switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
     74   default:
     75     llvm_unreachable("Could not map int to register");
     76   case 0: return Mips::MSAIR;
     77   case 1: return Mips::MSACSR;
     78   case 2: return Mips::MSAAccess;
     79   case 3: return Mips::MSASave;
     80   case 4: return Mips::MSAModify;
     81   case 5: return Mips::MSARequest;
     82   case 6: return Mips::MSAMap;
     83   case 7: return Mips::MSAUnmap;
     84   }
     85 }
     86 
     87 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
     88                                                 const MachineInstr& MI) {
     89   unsigned DstReg = 0, ZeroReg = 0;
     90 
     91   // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
     92   if ((MI.getOpcode() == Mips::ADDiu) &&
     93       (MI.getOperand(1).getReg() == Mips::ZERO) &&
     94       (MI.getOperand(2).getImm() == 0)) {
     95     DstReg = MI.getOperand(0).getReg();
     96     ZeroReg = Mips::ZERO;
     97   } else if ((MI.getOpcode() == Mips::DADDiu) &&
     98              (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
     99              (MI.getOperand(2).getImm() == 0)) {
    100     DstReg = MI.getOperand(0).getReg();
    101     ZeroReg = Mips::ZERO_64;
    102   }
    103 
    104   if (!DstReg)
    105     return false;
    106 
    107   // Replace uses with ZeroReg.
    108   for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
    109        E = MRI->use_end(); U != E;) {
    110     MachineOperand &MO = *U;
    111     unsigned OpNo = U.getOperandNo();
    112     MachineInstr *MI = MO.getParent();
    113     ++U;
    114 
    115     // Do not replace if it is a phi's operand or is tied to def operand.
    116     if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
    117       continue;
    118 
    119     // Also, we have to check that the register class of the operand
    120     // contains the zero register.
    121     if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
    122       continue;
    123 
    124     MO.setReg(ZeroReg);
    125   }
    126 
    127   return true;
    128 }
    129 
    130 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
    131   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
    132 
    133   if (!MipsFI->globalBaseRegSet())
    134     return;
    135 
    136   MachineBasicBlock &MBB = MF.front();
    137   MachineBasicBlock::iterator I = MBB.begin();
    138   MachineRegisterInfo &RegInfo = MF.getRegInfo();
    139   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
    140   DebugLoc DL;
    141   unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
    142   const TargetRegisterClass *RC;
    143   const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
    144   RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
    145 
    146   V0 = RegInfo.createVirtualRegister(RC);
    147   V1 = RegInfo.createVirtualRegister(RC);
    148 
    149   if (ABI.IsN64()) {
    150     MF.getRegInfo().addLiveIn(Mips::T9_64);
    151     MBB.addLiveIn(Mips::T9_64);
    152 
    153     // lui $v0, %hi(%neg(%gp_rel(fname)))
    154     // daddu $v1, $v0, $t9
    155     // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
    156     const GlobalValue *FName = MF.getFunction();
    157     BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
    158       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
    159     BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
    160       .addReg(Mips::T9_64);
    161     BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
    162       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
    163     return;
    164   }
    165 
    166   if (!MF.getTarget().isPositionIndependent()) {
    167     // Set global register to __gnu_local_gp.
    168     //
    169     // lui   $v0, %hi(__gnu_local_gp)
    170     // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
    171     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
    172       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
    173     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
    174       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
    175     return;
    176   }
    177 
    178   MF.getRegInfo().addLiveIn(Mips::T9);
    179   MBB.addLiveIn(Mips::T9);
    180 
    181   if (ABI.IsN32()) {
    182     // lui $v0, %hi(%neg(%gp_rel(fname)))
    183     // addu $v1, $v0, $t9
    184     // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
    185     const GlobalValue *FName = MF.getFunction();
    186     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
    187       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
    188     BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
    189     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
    190       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
    191     return;
    192   }
    193 
    194   assert(ABI.IsO32());
    195 
    196   // For O32 ABI, the following instruction sequence is emitted to initialize
    197   // the global base register:
    198   //
    199   //  0. lui   $2, %hi(_gp_disp)
    200   //  1. addiu $2, $2, %lo(_gp_disp)
    201   //  2. addu  $globalbasereg, $2, $t9
    202   //
    203   // We emit only the last instruction here.
    204   //
    205   // GNU linker requires that the first two instructions appear at the beginning
    206   // of a function and no instructions be inserted before or between them.
    207   // The two instructions are emitted during lowering to MC layer in order to
    208   // avoid any reordering.
    209   //
    210   // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
    211   // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
    212   // reads it.
    213   MF.getRegInfo().addLiveIn(Mips::V0);
    214   MBB.addLiveIn(Mips::V0);
    215   BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
    216     .addReg(Mips::V0).addReg(Mips::T9);
    217 }
    218 
    219 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
    220   initGlobalBaseReg(MF);
    221 
    222   MachineRegisterInfo *MRI = &MF.getRegInfo();
    223 
    224   for (auto &MBB: MF) {
    225     for (auto &MI: MBB) {
    226       switch (MI.getOpcode()) {
    227       case Mips::RDDSP:
    228         addDSPCtrlRegOperands(false, MI, MF);
    229         break;
    230       case Mips::WRDSP:
    231         addDSPCtrlRegOperands(true, MI, MF);
    232         break;
    233       default:
    234         replaceUsesWithZeroReg(MRI, MI);
    235       }
    236     }
    237   }
    238 }
    239 
    240 void MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
    241                                         SDValue CmpLHS, const SDLoc &DL,
    242                                         SDNode *Node) const {
    243   unsigned Opc = InFlag.getOpcode(); (void)Opc;
    244 
    245   assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
    246           (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
    247          "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
    248 
    249   unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
    250   if (Subtarget->isGP64bit()) {
    251     SLTuOp = Mips::SLTu64;
    252     ADDuOp = Mips::DADDu;
    253   }
    254 
    255   SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
    256   SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
    257   EVT VT = LHS.getValueType();
    258 
    259   SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
    260 
    261   if (Subtarget->isGP64bit()) {
    262     // On 64-bit targets, sltu produces an i64 but our backend currently says
    263     // that SLTu64 produces an i32. We need to fix this in the long run but for
    264     // now, just make the DAG type-correct by asserting the upper bits are zero.
    265     Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
    266                                    CurDAG->getTargetConstant(0, DL, VT),
    267                                    SDValue(Carry, 0),
    268                                    CurDAG->getTargetConstant(Mips::sub_32, DL,
    269                                                              VT));
    270   }
    271 
    272   // Generate a second addition only if we know that RHS is not a
    273   // constant-zero node.
    274   SDNode *AddCarry = Carry;
    275   ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
    276   if (!C || C->getZExtValue())
    277     AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);
    278 
    279   CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(AddCarry, 0));
    280 }
    281 
    282 /// Match frameindex
    283 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
    284                                               SDValue &Offset) const {
    285   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
    286     EVT ValTy = Addr.getValueType();
    287 
    288     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
    289     Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
    290     return true;
    291   }
    292   return false;
    293 }
    294 
    295 /// Match frameindex+offset and frameindex|offset
    296 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
    297                                                     SDValue &Offset,
    298                                                     unsigned OffsetBits) const {
    299   if (CurDAG->isBaseWithConstantOffset(Addr)) {
    300     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
    301     if (isIntN(OffsetBits, CN->getSExtValue())) {
    302       EVT ValTy = Addr.getValueType();
    303 
    304       // If the first operand is a FI, get the TargetFI Node
    305       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
    306                                   (Addr.getOperand(0)))
    307         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
    308       else
    309         Base = Addr.getOperand(0);
    310 
    311       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
    312                                          ValTy);
    313       return true;
    314     }
    315   }
    316   return false;
    317 }
    318 
    319 /// ComplexPattern used on MipsInstrInfo
    320 /// Used on Mips Load/Store instructions
    321 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
    322                                           SDValue &Offset) const {
    323   // if Address is FI, get the TargetFrameIndex.
    324   if (selectAddrFrameIndex(Addr, Base, Offset))
    325     return true;
    326 
    327   // on PIC code Load GA
    328   if (Addr.getOpcode() == MipsISD::Wrapper) {
    329     Base   = Addr.getOperand(0);
    330     Offset = Addr.getOperand(1);
    331     return true;
    332   }
    333 
    334   if (!TM.isPositionIndependent()) {
    335     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
    336         Addr.getOpcode() == ISD::TargetGlobalAddress))
    337       return false;
    338   }
    339 
    340   // Addresses of the form FI+const or FI|const
    341   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
    342     return true;
    343 
    344   // Operand is a result from an ADD.
    345   if (Addr.getOpcode() == ISD::ADD) {
    346     // When loading from constant pools, load the lower address part in
    347     // the instruction itself. Example, instead of:
    348     //  lui $2, %hi($CPI1_0)
    349     //  addiu $2, $2, %lo($CPI1_0)
    350     //  lwc1 $f0, 0($2)
    351     // Generate:
    352     //  lui $2, %hi($CPI1_0)
    353     //  lwc1 $f0, %lo($CPI1_0)($2)
    354     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
    355         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
    356       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
    357       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
    358           isa<JumpTableSDNode>(Opnd0)) {
    359         Base = Addr.getOperand(0);
    360         Offset = Opnd0;
    361         return true;
    362       }
    363     }
    364   }
    365 
    366   return false;
    367 }
    368 
    369 /// ComplexPattern used on MipsInstrInfo
    370 /// Used on Mips Load/Store instructions
    371 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
    372                                            SDValue &Offset) const {
    373   Base = Addr;
    374   Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
    375   return true;
    376 }
    377 
    378 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
    379                                        SDValue &Offset) const {
    380   return selectAddrRegImm(Addr, Base, Offset) ||
    381     selectAddrDefault(Addr, Base, Offset);
    382 }
    383 
    384 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
    385                                            SDValue &Offset) const {
    386   if (selectAddrFrameIndex(Addr, Base, Offset))
    387     return true;
    388 
    389   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
    390     return true;
    391 
    392   return false;
    393 }
    394 
    395 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
    396                                             SDValue &Offset) const {
    397   if (selectAddrFrameIndex(Addr, Base, Offset))
    398     return true;
    399 
    400   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
    401     return true;
    402 
    403   return false;
    404 }
    405 
    406 /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
    407 bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
    408                                             SDValue &Offset) const {
    409   if (selectAddrFrameIndex(Addr, Base, Offset))
    410     return true;
    411 
    412   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
    413     return true;
    414 
    415   return false;
    416 }
    417 
    418 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
    419 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
    420                                             SDValue &Offset) const {
    421   if (selectAddrFrameIndex(Addr, Base, Offset))
    422     return true;
    423 
    424   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
    425     return true;
    426 
    427   return false;
    428 }
    429 
    430 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
    431                                             SDValue &Offset) const {
    432   if (selectAddrFrameIndex(Addr, Base, Offset))
    433     return true;
    434 
    435   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
    436     return true;
    437 
    438   return false;
    439 }
    440 
    441 bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
    442                                          SDValue &Offset) const {
    443   return selectAddrRegImm11(Addr, Base, Offset) ||
    444     selectAddrDefault(Addr, Base, Offset);
    445 }
    446 
    447 bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
    448                                          SDValue &Offset) const {
    449   return selectAddrRegImm12(Addr, Base, Offset) ||
    450     selectAddrDefault(Addr, Base, Offset);
    451 }
    452 
    453 bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
    454                                          SDValue &Offset) const {
    455   return selectAddrRegImm16(Addr, Base, Offset) ||
    456     selectAddrDefault(Addr, Base, Offset);
    457 }
    458 
    459 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
    460                                              SDValue &Offset) const {
    461   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
    462     if (isa<FrameIndexSDNode>(Base))
    463       return false;
    464 
    465     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
    466       unsigned CnstOff = CN->getZExtValue();
    467       return (CnstOff == (CnstOff & 0x3c));
    468     }
    469 
    470     return false;
    471   }
    472 
    473   // For all other cases where "lw" would be selected, don't select "lw16"
    474   // because it would result in additional instructions to prepare operands.
    475   if (selectAddrRegImm(Addr, Base, Offset))
    476     return false;
    477 
    478   return selectAddrDefault(Addr, Base, Offset);
    479 }
    480 
    481 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
    482                                           SDValue &Offset) const {
    483   if (selectAddrRegImm10(Addr, Base, Offset))
    484     return true;
    485 
    486   if (selectAddrDefault(Addr, Base, Offset))
    487     return true;
    488 
    489   return false;
    490 }
    491 
    492 // Select constant vector splats.
    493 //
    494 // Returns true and sets Imm if:
    495 // * MSA is enabled
    496 // * N is a ISD::BUILD_VECTOR representing a constant splat
    497 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
    498                                       unsigned MinSizeInBits) const {
    499   if (!Subtarget->hasMSA())
    500     return false;
    501 
    502   BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
    503 
    504   if (!Node)
    505     return false;
    506 
    507   APInt SplatValue, SplatUndef;
    508   unsigned SplatBitSize;
    509   bool HasAnyUndefs;
    510 
    511   if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
    512                              MinSizeInBits, !Subtarget->isLittle()))
    513     return false;
    514 
    515   Imm = SplatValue;
    516 
    517   return true;
    518 }
    519 
    520 // Select constant vector splats.
    521 //
    522 // In addition to the requirements of selectVSplat(), this function returns
    523 // true and sets Imm if:
    524 // * The splat value is the same width as the elements of the vector
    525 // * The splat value fits in an integer with the specified signed-ness and
    526 //   width.
    527 //
    528 // This function looks through ISD::BITCAST nodes.
    529 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    530 //       sometimes a shuffle in big-endian mode.
    531 //
    532 // It's worth noting that this function is not used as part of the selection
    533 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
    534 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
    535 // MipsSEDAGToDAGISel::selectNode.
    536 bool MipsSEDAGToDAGISel::
    537 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
    538                    unsigned ImmBitSize) const {
    539   APInt ImmValue;
    540   EVT EltTy = N->getValueType(0).getVectorElementType();
    541 
    542   if (N->getOpcode() == ISD::BITCAST)
    543     N = N->getOperand(0);
    544 
    545   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
    546       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    547 
    548     if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
    549         (!Signed && ImmValue.isIntN(ImmBitSize))) {
    550       Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
    551       return true;
    552     }
    553   }
    554 
    555   return false;
    556 }
    557 
    558 // Select constant vector splats.
    559 bool MipsSEDAGToDAGISel::
    560 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
    561   return selectVSplatCommon(N, Imm, false, 1);
    562 }
    563 
    564 bool MipsSEDAGToDAGISel::
    565 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
    566   return selectVSplatCommon(N, Imm, false, 2);
    567 }
    568 
    569 bool MipsSEDAGToDAGISel::
    570 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
    571   return selectVSplatCommon(N, Imm, false, 3);
    572 }
    573 
    574 // Select constant vector splats.
    575 bool MipsSEDAGToDAGISel::
    576 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
    577   return selectVSplatCommon(N, Imm, false, 4);
    578 }
    579 
    580 // Select constant vector splats.
    581 bool MipsSEDAGToDAGISel::
    582 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
    583   return selectVSplatCommon(N, Imm, false, 5);
    584 }
    585 
    586 // Select constant vector splats.
    587 bool MipsSEDAGToDAGISel::
    588 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
    589   return selectVSplatCommon(N, Imm, false, 6);
    590 }
    591 
    592 // Select constant vector splats.
    593 bool MipsSEDAGToDAGISel::
    594 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
    595   return selectVSplatCommon(N, Imm, false, 8);
    596 }
    597 
    598 // Select constant vector splats.
    599 bool MipsSEDAGToDAGISel::
    600 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
    601   return selectVSplatCommon(N, Imm, true, 5);
    602 }
    603 
    604 // Select constant vector splats whose value is a power of 2.
    605 //
    606 // In addition to the requirements of selectVSplat(), this function returns
    607 // true and sets Imm if:
    608 // * The splat value is the same width as the elements of the vector
    609 // * The splat value is a power of two.
    610 //
    611 // This function looks through ISD::BITCAST nodes.
    612 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    613 //       sometimes a shuffle in big-endian mode.
    614 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
    615   APInt ImmValue;
    616   EVT EltTy = N->getValueType(0).getVectorElementType();
    617 
    618   if (N->getOpcode() == ISD::BITCAST)
    619     N = N->getOperand(0);
    620 
    621   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
    622       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    623     int32_t Log2 = ImmValue.exactLogBase2();
    624 
    625     if (Log2 != -1) {
    626       Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
    627       return true;
    628     }
    629   }
    630 
    631   return false;
    632 }
    633 
    634 // Select constant vector splats whose value only has a consecutive sequence
    635 // of left-most bits set (e.g. 0b11...1100...00).
    636 //
    637 // In addition to the requirements of selectVSplat(), this function returns
    638 // true and sets Imm if:
    639 // * The splat value is the same width as the elements of the vector
    640 // * The splat value is a consecutive sequence of left-most bits.
    641 //
    642 // This function looks through ISD::BITCAST nodes.
    643 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    644 //       sometimes a shuffle in big-endian mode.
    645 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
    646   APInt ImmValue;
    647   EVT EltTy = N->getValueType(0).getVectorElementType();
    648 
    649   if (N->getOpcode() == ISD::BITCAST)
    650     N = N->getOperand(0);
    651 
    652   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
    653       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    654     // Extract the run of set bits starting with bit zero from the bitwise
    655     // inverse of ImmValue, and test that the inverse of this is the same
    656     // as the original value.
    657     if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
    658 
    659       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), SDLoc(N),
    660                                       EltTy);
    661       return true;
    662     }
    663   }
    664 
    665   return false;
    666 }
    667 
    668 // Select constant vector splats whose value only has a consecutive sequence
    669 // of right-most bits set (e.g. 0b00...0011...11).
    670 //
    671 // In addition to the requirements of selectVSplat(), this function returns
    672 // true and sets Imm if:
    673 // * The splat value is the same width as the elements of the vector
    674 // * The splat value is a consecutive sequence of right-most bits.
    675 //
    676 // This function looks through ISD::BITCAST nodes.
    677 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
    678 //       sometimes a shuffle in big-endian mode.
    679 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
    680   APInt ImmValue;
    681   EVT EltTy = N->getValueType(0).getVectorElementType();
    682 
    683   if (N->getOpcode() == ISD::BITCAST)
    684     N = N->getOperand(0);
    685 
    686   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
    687       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    688     // Extract the run of set bits starting with bit zero, and test that the
    689     // result is the same as the original value
    690     if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
    691       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), SDLoc(N),
    692                                       EltTy);
    693       return true;
    694     }
    695   }
    696 
    697   return false;
    698 }
    699 
    700 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
    701                                                  SDValue &Imm) const {
    702   APInt ImmValue;
    703   EVT EltTy = N->getValueType(0).getVectorElementType();
    704 
    705   if (N->getOpcode() == ISD::BITCAST)
    706     N = N->getOperand(0);
    707 
    708   if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
    709       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
    710     int32_t Log2 = (~ImmValue).exactLogBase2();
    711 
    712     if (Log2 != -1) {
    713       Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
    714       return true;
    715     }
    716   }
    717 
    718   return false;
    719 }
    720 
    721 bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
    722   unsigned Opcode = Node->getOpcode();
    723   SDLoc DL(Node);
    724 
    725   ///
    726   // Instruction Selection not handled by the auto-generated
    727   // tablegen selection should be handled here.
    728   ///
    729   switch(Opcode) {
    730   default: break;
    731 
    732   case ISD::SUBE: {
    733     SDValue InFlag = Node->getOperand(2);
    734     unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
    735     selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
    736     return true;
    737   }
    738 
    739   case ISD::ADDE: {
    740     if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
    741       break;
    742     SDValue InFlag = Node->getOperand(2);
    743     unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
    744     selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
    745     return true;
    746   }
    747 
    748   case ISD::ConstantFP: {
    749     ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
    750     if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
    751       if (Subtarget->isGP64bit()) {
    752         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
    753                                               Mips::ZERO_64, MVT::i64);
    754         ReplaceNode(Node,
    755                     CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
    756       } else if (Subtarget->isFP64bit()) {
    757         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
    758                                               Mips::ZERO, MVT::i32);
    759         ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
    760                                                  MVT::f64, Zero, Zero));
    761       } else {
    762         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
    763                                               Mips::ZERO, MVT::i32);
    764         ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL,
    765                                                  MVT::f64, Zero, Zero));
    766       }
    767       return true;
    768     }
    769     break;
    770   }
    771 
    772   case ISD::Constant: {
    773     const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
    774     unsigned Size = CN->getValueSizeInBits(0);
    775 
    776     if (Size == 32)
    777       break;
    778 
    779     MipsAnalyzeImmediate AnalyzeImm;
    780     int64_t Imm = CN->getSExtValue();
    781 
    782     const MipsAnalyzeImmediate::InstSeq &Seq =
    783       AnalyzeImm.Analyze(Imm, Size, false);
    784 
    785     MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
    786     SDLoc DL(CN);
    787     SDNode *RegOpnd;
    788     SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
    789                                                 DL, MVT::i64);
    790 
    791     // The first instruction can be a LUi which is different from other
    792     // instructions (ADDiu, ORI and SLL) in that it does not have a register
    793     // operand.
    794     if (Inst->Opc == Mips::LUi64)
    795       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
    796     else
    797       RegOpnd =
    798         CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
    799                                CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
    800                                ImmOpnd);
    801 
    802     // The remaining instructions in the sequence are handled here.
    803     for (++Inst; Inst != Seq.end(); ++Inst) {
    804       ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
    805                                           MVT::i64);
    806       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
    807                                        SDValue(RegOpnd, 0), ImmOpnd);
    808     }
    809 
    810     ReplaceNode(Node, RegOpnd);
    811     return true;
    812   }
    813 
    814   case ISD::INTRINSIC_W_CHAIN: {
    815     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
    816     default:
    817       break;
    818 
    819     case Intrinsic::mips_cfcmsa: {
    820       SDValue ChainIn = Node->getOperand(0);
    821       SDValue RegIdx = Node->getOperand(2);
    822       SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
    823                                            getMSACtrlReg(RegIdx), MVT::i32);
    824       ReplaceNode(Node, Reg.getNode());
    825       return true;
    826     }
    827     }
    828     break;
    829   }
    830 
    831   case ISD::INTRINSIC_WO_CHAIN: {
    832     switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
    833     default:
    834       break;
    835 
    836     case Intrinsic::mips_move_v:
    837       // Like an assignment but will always produce a move.v even if
    838       // unnecessary.
    839       ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
    840                                                Node->getValueType(0),
    841                                                Node->getOperand(1)));
    842       return true;
    843     }
    844     break;
    845   }
    846 
    847   case ISD::INTRINSIC_VOID: {
    848     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
    849     default:
    850       break;
    851 
    852     case Intrinsic::mips_ctcmsa: {
    853       SDValue ChainIn = Node->getOperand(0);
    854       SDValue RegIdx  = Node->getOperand(2);
    855       SDValue Value   = Node->getOperand(3);
    856       SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
    857                                               getMSACtrlReg(RegIdx), Value);
    858       ReplaceNode(Node, ChainOut.getNode());
    859       return true;
    860     }
    861     }
    862     break;
    863   }
    864 
    865   case MipsISD::ThreadPointer: {
    866     EVT PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
    867     unsigned RdhwrOpc, DestReg;
    868 
    869     if (PtrVT == MVT::i32) {
    870       RdhwrOpc = Mips::RDHWR;
    871       DestReg = Mips::V1;
    872     } else {
    873       RdhwrOpc = Mips::RDHWR64;
    874       DestReg = Mips::V1_64;
    875     }
    876 
    877     SDNode *Rdhwr =
    878       CurDAG->getMachineNode(RdhwrOpc, DL,
    879                              Node->getValueType(0),
    880                              CurDAG->getRegister(Mips::HWR29, MVT::i32));
    881     SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
    882                                          SDValue(Rdhwr, 0));
    883     SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
    884     ReplaceNode(Node, ResNode.getNode());
    885     return true;
    886   }
    887 
    888   case ISD::BUILD_VECTOR: {
    889     // Select appropriate ldi.[bhwd] instructions for constant splats of
    890     // 128-bit when MSA is enabled. Fixup any register class mismatches that
    891     // occur as a result.
    892     //
    893     // This allows the compiler to use a wider range of immediates than would
    894     // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
    895     // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
    896     // 0x01010101 } without using a constant pool. This would be sub-optimal
    897     // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
    898     // same set/ of registers. Similarly, ldi.h isn't capable of producing {
    899     // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
    900 
    901     BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
    902     APInt SplatValue, SplatUndef;
    903     unsigned SplatBitSize;
    904     bool HasAnyUndefs;
    905     unsigned LdiOp;
    906     EVT ResVecTy = BVN->getValueType(0);
    907     EVT ViaVecTy;
    908 
    909     if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
    910       return false;
    911 
    912     if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
    913                               HasAnyUndefs, 8,
    914                               !Subtarget->isLittle()))
    915       return false;
    916 
    917     switch (SplatBitSize) {
    918     default:
    919       return false;
    920     case 8:
    921       LdiOp = Mips::LDI_B;
    922       ViaVecTy = MVT::v16i8;
    923       break;
    924     case 16:
    925       LdiOp = Mips::LDI_H;
    926       ViaVecTy = MVT::v8i16;
    927       break;
    928     case 32:
    929       LdiOp = Mips::LDI_W;
    930       ViaVecTy = MVT::v4i32;
    931       break;
    932     case 64:
    933       LdiOp = Mips::LDI_D;
    934       ViaVecTy = MVT::v2i64;
    935       break;
    936     }
    937 
    938     if (!SplatValue.isSignedIntN(10))
    939       return false;
    940 
    941     SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
    942                                             ViaVecTy.getVectorElementType());
    943 
    944     SDNode *Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
    945 
    946     if (ResVecTy != ViaVecTy) {
    947       // If LdiOp is writing to a different register class to ResVecTy, then
    948       // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
    949       // since the source and destination register sets contain the same
    950       // registers.
    951       const TargetLowering *TLI = getTargetLowering();
    952       MVT ResVecTySimple = ResVecTy.getSimpleVT();
    953       const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
    954       Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
    955                                    ResVecTy, SDValue(Res, 0),
    956                                    CurDAG->getTargetConstant(RC->getID(), DL,
    957                                                              MVT::i32));
    958     }
    959 
    960     ReplaceNode(Node, Res);
    961     return true;
    962   }
    963 
    964   }
    965 
    966   return false;
    967 }
    968 
    969 bool MipsSEDAGToDAGISel::
    970 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
    971                              std::vector<SDValue> &OutOps) {
    972   SDValue Base, Offset;
    973 
    974   switch(ConstraintID) {
    975   default:
    976     llvm_unreachable("Unexpected asm memory constraint");
    977   // All memory constraints can at least accept raw pointers.
    978   case InlineAsm::Constraint_i:
    979     OutOps.push_back(Op);
    980     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
    981     return false;
    982   case InlineAsm::Constraint_m:
    983     if (selectAddrRegImm16(Op, Base, Offset)) {
    984       OutOps.push_back(Base);
    985       OutOps.push_back(Offset);
    986       return false;
    987     }
    988     OutOps.push_back(Op);
    989     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
    990     return false;
    991   case InlineAsm::Constraint_R:
    992     // The 'R' constraint is supposed to be much more complicated than this.
    993     // However, it's becoming less useful due to architectural changes and
    994     // ought to be replaced by other constraints such as 'ZC'.
    995     // For now, support 9-bit signed offsets which is supportable by all
    996     // subtargets for all instructions.
    997     if (selectAddrRegImm9(Op, Base, Offset)) {
    998       OutOps.push_back(Base);
    999       OutOps.push_back(Offset);
   1000       return false;
   1001     }
   1002     OutOps.push_back(Op);
   1003     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
   1004     return false;
   1005   case InlineAsm::Constraint_ZC:
   1006     // ZC matches whatever the pref, ll, and sc instructions can handle for the
   1007     // given subtarget.
   1008     if (Subtarget->inMicroMipsMode()) {
   1009       // On microMIPS, they can handle 12-bit offsets.
   1010       if (selectAddrRegImm12(Op, Base, Offset)) {
   1011         OutOps.push_back(Base);
   1012         OutOps.push_back(Offset);
   1013         return false;
   1014       }
   1015     } else if (Subtarget->hasMips32r6()) {
   1016       // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
   1017       if (selectAddrRegImm9(Op, Base, Offset)) {
   1018         OutOps.push_back(Base);
   1019         OutOps.push_back(Offset);
   1020         return false;
   1021       }
   1022     } else if (selectAddrRegImm16(Op, Base, Offset)) {
   1023       // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
   1024       OutOps.push_back(Base);
   1025       OutOps.push_back(Offset);
   1026       return false;
   1027     }
   1028     // In all cases, 0-bit offsets are acceptable.
   1029     OutOps.push_back(Op);
   1030     OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
   1031     return false;
   1032   }
   1033   return true;
   1034 }
   1035 
   1036 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
   1037                                         CodeGenOpt::Level OptLevel) {
   1038   return new MipsSEDAGToDAGISel(TM, OptLevel);
   1039 }
   1040