| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| RegisterInfoEmitter.h | 34 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
37 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
41 CodeGenRegBank &Bank);
45 CodeGenRegBank &Bank);
|
| RegisterInfoEmitter.cpp | 31 CodeGenTarget &Target, CodeGenRegBank &Bank) {
32 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
60 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| RegisterBankEmitter.cpp | 1 //===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//
11 // register bank for a code generator.
24 #define DEBUG_TYPE "register-bank-emitter"
31 /// A vector of register classes that are included in the register bank.
37 /// The register classes that are covered by the register bank.
47 /// Get the human-readable name for the bank.
72 /// Add a register class to the bank without duplicates.
136 for (const auto &Bank : Banks)
137 OS << " " << Bank.getEnumeratorName() << ",\n";
155 /// Visit each register class belonging to the given register bank
[all...] |
| RegisterInfoEmitter.cpp | 68 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
71 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
75 CodeGenRegBank &Bank);
79 CodeGenRegBank &Bank);
104 CodeGenTarget &Target, CodeGenRegBank &Bank) {
105 const auto &Registers = Bank.getRegisters();
136 const auto &RegisterClasses = Bank.getRegClasses();
171 auto &SubRegIndices = Bank.getSubRegIndices();
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/Library/DebugAgentTimerLib/ |
| DebugAgentTimerLib.c | 39 UINTN Bank;
45 Bank = gVector / 32;
48 MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
56 UINTN Bank;
59 Bank = gVector / 32;
62 MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/InterruptDxe/ |
| HardwareInterrupt.c | 126 UINTN Bank;
134 Bank = Source / 32;
137 MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
160 UINTN Bank;
168 Bank = Source / 32;
171 MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
197 UINTN Bank;
209 Bank = Source / 32;
212 if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| AMDGPURegisterBankInfo.cpp | 197 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
198 if (Bank && Bank->getID() != AMDGPU::SGPRRegBankID)
283 const RegisterBank *Bank = getRegBank(Reg, MRI, TRI);
284 return Bank ? Bank->getID() : Default;
344 unsigned Bank = isSALUMapping(MI) ?
349 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
350 // Op1 and Dst should use the same register bank.
352 OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize)
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/ |
| Lan91xDxe.c | 75 UINT8 BankSel; // Currently selected register bank
209 // Select the proper I/O bank
217 UINT8 Bank;
219 Bank = RegisterToBank (Register);
221 // Select the proper I/O bank
222 if (LanDriver->BankSel != Bank) {
223 MmioWrite16 (LanDriver->IoBase + LAN91X_BANK_OFFSET, Bank);
224 LanDriver->BankSel = Bank;
238 // Select the proper I/O bank
257 // Select the proper I/O bank
[all...] |
| Lan91xDxeHw.h | 21 #define MakeRegister(Bank, Offset) (((Bank) << 8) | (Offset))
30 #define LAN91X_BANK_OFFSET 0xe // Bank Select Register (all banks)
|
| /external/brotli/c/enc/ |
| hash_forgetful_chain_inc.h | 15 share a storage "bank". When more than "bank size" chain nodes are added,
43 typedef struct FN(Bank) {
45 } FN(Bank);
52 FN(Bank) banks[NUM_BANKS];
106 const size_t bank = key & (NUM_BANKS - 1); local
107 const size_t idx = self->free_slot_idx[bank]++ & (BANK_SIZE - 1);
111 self->banks[bank].slots[idx].delta = (uint16_t)delta;
112 self->banks[bank].slots[idx].next = self->head[key];
204 const size_t bank = key & (NUM_BANKS - 1) local
[all...] |
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 55 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
58 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
62 CodeGenRegBank &Bank);
66 CodeGenRegBank &Bank);
89 CodeGenTarget &Target, CodeGenRegBank &Bank) {
90 const auto &Registers = Bank.getRegisters();
122 const auto &RegisterClasses = Bank.getRegClasses();
157 auto &SubRegIndices = Bank.getSubRegIndices();
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/ |
| Iscp.h | 90 UINT32 Bank; ///< DRAM Bank
|
| /external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| README.lsch3 | 76 ----------------------------------------- ----> 0x5_84D0_0000 | Bank
97 | Debug Server FW (2M) | | Bank
|
| /device/linaro/bootloader/edk2/MdePkg/Include/Guid/ |
| Cper.h | 841 UINT16 Bank;
[all...] |
| /build/make/tools/droiddoc/templates-ndk/assets/js/ |
| android_3p-bundle.js | [all...] |
| /external/doclava/res/assets/templates-sdk/assets/js/ |
| android_3p-bundle.js | [all...] |
