1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend is responsible for emitting a description of a target 11 // register file for a code generator. It uses instances of the Register, 12 // RegisterAliases, and RegisterClass classes to gather this information. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenRegisters.h" 17 #include "CodeGenTarget.h" 18 #include "SequenceToOffsetTable.h" 19 #include "Types.h" 20 #include "llvm/ADT/ArrayRef.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/STLExtras.h" 23 #include "llvm/ADT/SetVector.h" 24 #include "llvm/ADT/SmallVector.h" 25 #include "llvm/ADT/SparseBitVector.h" 26 #include "llvm/ADT/Twine.h" 27 #include "llvm/Support/Casting.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Support/Format.h" 30 #include "llvm/Support/MachineValueType.h" 31 #include "llvm/Support/raw_ostream.h" 32 #include "llvm/TableGen/Error.h" 33 #include "llvm/TableGen/Record.h" 34 #include "llvm/TableGen/SetTheory.h" 35 #include "llvm/TableGen/TableGenBackend.h" 36 #include <algorithm> 37 #include <cassert> 38 #include <cstddef> 39 #include <cstdint> 40 #include <deque> 41 #include <iterator> 42 #include <set> 43 #include <string> 44 #include <vector> 45 46 using namespace llvm; 47 48 cl::OptionCategory RegisterInfoCat("Options for -gen-register-info"); 49 50 static cl::opt<bool> 51 RegisterInfoDebug("register-info-debug", cl::init(false), 52 cl::desc("Dump register information to help debugging"), 53 cl::cat(RegisterInfoCat)); 54 55 namespace { 56 57 class RegisterInfoEmitter { 58 CodeGenTarget Target; 59 RecordKeeper &Records; 60 61 public: 62 RegisterInfoEmitter(RecordKeeper &R) : Target(R), Records(R) { 63 CodeGenRegBank &RegBank = Target.getRegBank(); 64 RegBank.computeDerivedInfo(); 65 } 66 67 // runEnums - Print out enum values for all of the registers. 68 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 69 70 // runMCDesc - Print out MC register descriptions. 71 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 72 73 // runTargetHeader - Emit a header fragment for the register info emitter. 74 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 75 CodeGenRegBank &Bank); 76 77 // runTargetDesc - Output the target register and register file descriptions. 78 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 79 CodeGenRegBank &Bank); 80 81 // run - Output the register file description. 82 void run(raw_ostream &o); 83 84 void debugDump(raw_ostream &OS); 85 86 private: 87 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 88 bool isCtor); 89 void EmitRegMappingTables(raw_ostream &o, 90 const std::deque<CodeGenRegister> &Regs, 91 bool isCtor); 92 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 93 const std::string &ClassName); 94 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 95 const std::string &ClassName); 96 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, 97 const std::string &ClassName); 98 }; 99 100 } // end anonymous namespace 101 102 // runEnums - Print out enum values for all of the registers. 103 void RegisterInfoEmitter::runEnums(raw_ostream &OS, 104 CodeGenTarget &Target, CodeGenRegBank &Bank) { 105 const auto &Registers = Bank.getRegisters(); 106 107 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 108 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 109 110 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 111 112 emitSourceFileHeader("Target Register Enum Values", OS); 113 114 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 115 OS << "#undef GET_REGINFO_ENUM\n\n"; 116 117 OS << "namespace llvm {\n\n"; 118 119 OS << "class MCRegisterClass;\n" 120 << "extern const MCRegisterClass " << Target.getName() 121 << "MCRegisterClasses[];\n\n"; 122 123 if (!Namespace.empty()) 124 OS << "namespace " << Namespace << " {\n"; 125 OS << "enum {\n NoRegister,\n"; 126 127 for (const auto &Reg : Registers) 128 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 129 assert(Registers.size() == Registers.back().EnumValue && 130 "Register enum value mismatch!"); 131 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 132 OS << "};\n"; 133 if (!Namespace.empty()) 134 OS << "} // end namespace " << Namespace << "\n"; 135 136 const auto &RegisterClasses = Bank.getRegClasses(); 137 if (!RegisterClasses.empty()) { 138 139 // RegisterClass enums are stored as uint16_t in the tables. 140 assert(RegisterClasses.size() <= 0xffff && 141 "Too many register classes to fit in tables"); 142 143 OS << "\n// Register classes\n\n"; 144 if (!Namespace.empty()) 145 OS << "namespace " << Namespace << " {\n"; 146 OS << "enum {\n"; 147 for (const auto &RC : RegisterClasses) 148 OS << " " << RC.getName() << "RegClassID" 149 << " = " << RC.EnumValue << ",\n"; 150 OS << "\n };\n"; 151 if (!Namespace.empty()) 152 OS << "} // end namespace " << Namespace << "\n\n"; 153 } 154 155 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 156 // If the only definition is the default NoRegAltName, we don't need to 157 // emit anything. 158 if (RegAltNameIndices.size() > 1) { 159 OS << "\n// Register alternate name indices\n\n"; 160 if (!Namespace.empty()) 161 OS << "namespace " << Namespace << " {\n"; 162 OS << "enum {\n"; 163 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 164 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 165 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 166 OS << "};\n"; 167 if (!Namespace.empty()) 168 OS << "} // end namespace " << Namespace << "\n\n"; 169 } 170 171 auto &SubRegIndices = Bank.getSubRegIndices(); 172 if (!SubRegIndices.empty()) { 173 OS << "\n// Subregister indices\n\n"; 174 std::string Namespace = SubRegIndices.front().getNamespace(); 175 if (!Namespace.empty()) 176 OS << "namespace " << Namespace << " {\n"; 177 OS << "enum {\n NoSubRegister,\n"; 178 unsigned i = 0; 179 for (const auto &Idx : SubRegIndices) 180 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 181 OS << " NUM_TARGET_SUBREGS\n};\n"; 182 if (!Namespace.empty()) 183 OS << "} // end namespace " << Namespace << "\n\n"; 184 } 185 186 OS << "} // end namespace llvm\n\n"; 187 OS << "#endif // GET_REGINFO_ENUM\n\n"; 188 } 189 190 static void printInt(raw_ostream &OS, int Val) { 191 OS << Val; 192 } 193 194 void RegisterInfoEmitter:: 195 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 196 const std::string &ClassName) { 197 unsigned NumRCs = RegBank.getRegClasses().size(); 198 unsigned NumSets = RegBank.getNumRegPressureSets(); 199 200 OS << "/// Get the weight in units of pressure for this register class.\n" 201 << "const RegClassWeight &" << ClassName << "::\n" 202 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 203 << " static const RegClassWeight RCWeightTable[] = {\n"; 204 for (const auto &RC : RegBank.getRegClasses()) { 205 const CodeGenRegister::Vec &Regs = RC.getMembers(); 206 if (Regs.empty() || RC.Artificial) 207 OS << " {0, 0"; 208 else { 209 std::vector<unsigned> RegUnits; 210 RC.buildRegUnitSet(RegBank, RegUnits); 211 OS << " {" << (*Regs.begin())->getWeight(RegBank) 212 << ", " << RegBank.getRegUnitSetWeight(RegUnits); 213 } 214 OS << "}, \t// " << RC.getName() << "\n"; 215 } 216 OS << " };\n" 217 << " return RCWeightTable[RC->getID()];\n" 218 << "}\n\n"; 219 220 // Reasonable targets (not ARMv7) have unit weight for all units, so don't 221 // bother generating a table. 222 bool RegUnitsHaveUnitWeight = true; 223 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 224 UnitIdx < UnitEnd; ++UnitIdx) { 225 if (RegBank.getRegUnit(UnitIdx).Weight > 1) 226 RegUnitsHaveUnitWeight = false; 227 } 228 OS << "/// Get the weight in units of pressure for this register unit.\n" 229 << "unsigned " << ClassName << "::\n" 230 << "getRegUnitWeight(unsigned RegUnit) const {\n" 231 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 232 << " && \"invalid register unit\");\n"; 233 if (!RegUnitsHaveUnitWeight) { 234 OS << " static const uint8_t RUWeightTable[] = {\n "; 235 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 236 UnitIdx < UnitEnd; ++UnitIdx) { 237 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 238 assert(RU.Weight < 256 && "RegUnit too heavy"); 239 OS << RU.Weight << ", "; 240 } 241 OS << "};\n" 242 << " return RUWeightTable[RegUnit];\n"; 243 } 244 else { 245 OS << " // All register units have unit weight.\n" 246 << " return 1;\n"; 247 } 248 OS << "}\n\n"; 249 250 OS << "\n" 251 << "// Get the number of dimensions of register pressure.\n" 252 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 253 << " return " << NumSets << ";\n}\n\n"; 254 255 OS << "// Get the name of this register unit pressure set.\n" 256 << "const char *" << ClassName << "::\n" 257 << "getRegPressureSetName(unsigned Idx) const {\n" 258 << " static const char *const PressureNameTable[] = {\n"; 259 unsigned MaxRegUnitWeight = 0; 260 for (unsigned i = 0; i < NumSets; ++i ) { 261 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 262 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 263 OS << " \"" << RegUnits.Name << "\",\n"; 264 } 265 OS << " };\n" 266 << " return PressureNameTable[Idx];\n" 267 << "}\n\n"; 268 269 OS << "// Get the register unit pressure limit for this dimension.\n" 270 << "// This limit must be adjusted dynamically for reserved registers.\n" 271 << "unsigned " << ClassName << "::\n" 272 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const " 273 "{\n" 274 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32) 275 << " PressureLimitTable[] = {\n"; 276 for (unsigned i = 0; i < NumSets; ++i ) { 277 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 278 OS << " " << RegUnits.Weight << ", \t// " << i << ": " 279 << RegUnits.Name << "\n"; 280 } 281 OS << " };\n" 282 << " return PressureLimitTable[Idx];\n" 283 << "}\n\n"; 284 285 SequenceToOffsetTable<std::vector<int>> PSetsSeqs; 286 287 // This table may be larger than NumRCs if some register units needed a list 288 // of unit sets that did not correspond to a register class. 289 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 290 std::vector<std::vector<int>> PSets(NumRCUnitSets); 291 292 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 293 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 294 PSets[i].reserve(PSetIDs.size()); 295 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 296 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 297 PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order); 298 } 299 llvm::sort(PSets[i].begin(), PSets[i].end()); 300 PSetsSeqs.add(PSets[i]); 301 } 302 303 PSetsSeqs.layout(); 304 305 OS << "/// Table of pressure sets per register class or unit.\n" 306 << "static const int RCSetsTable[] = {\n"; 307 PSetsSeqs.emit(OS, printInt, "-1"); 308 OS << "};\n\n"; 309 310 OS << "/// Get the dimensions of register pressure impacted by this " 311 << "register class.\n" 312 << "/// Returns a -1 terminated array of pressure set IDs\n" 313 << "const int* " << ClassName << "::\n" 314 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 315 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 316 << " RCSetStartTable[] = {\n "; 317 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 318 OS << PSetsSeqs.get(PSets[i]) << ","; 319 } 320 OS << "};\n" 321 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 322 << "}\n\n"; 323 324 OS << "/// Get the dimensions of register pressure impacted by this " 325 << "register unit.\n" 326 << "/// Returns a -1 terminated array of pressure set IDs\n" 327 << "const int* " << ClassName << "::\n" 328 << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 329 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 330 << " && \"invalid register unit\");\n"; 331 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 332 << " RUSetStartTable[] = {\n "; 333 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 334 UnitIdx < UnitEnd; ++UnitIdx) { 335 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 336 << ","; 337 } 338 OS << "};\n" 339 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 340 << "}\n\n"; 341 } 342 343 void RegisterInfoEmitter::EmitRegMappingTables( 344 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 345 // Collect all information about dwarf register numbers 346 typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy; 347 DwarfRegNumsMapTy DwarfRegNums; 348 349 // First, just pull all provided information to the map 350 unsigned maxLength = 0; 351 for (auto &RE : Regs) { 352 Record *Reg = RE.TheDef; 353 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 354 maxLength = std::max((size_t)maxLength, RegNums.size()); 355 if (DwarfRegNums.count(Reg)) 356 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 357 getQualifiedName(Reg) + "specified multiple times"); 358 DwarfRegNums[Reg] = RegNums; 359 } 360 361 if (!maxLength) 362 return; 363 364 // Now we know maximal length of number list. Append -1's, where needed 365 for (DwarfRegNumsMapTy::iterator 366 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 367 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 368 I->second.push_back(-1); 369 370 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 371 372 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 373 374 // Emit reverse information about the dwarf register numbers. 375 for (unsigned j = 0; j < 2; ++j) { 376 for (unsigned i = 0, e = maxLength; i != e; ++i) { 377 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 378 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 379 OS << i << "Dwarf2L[]"; 380 381 if (!isCtor) { 382 OS << " = {\n"; 383 384 // Store the mapping sorted by the LLVM reg num so lookup can be done 385 // with a binary search. 386 std::map<uint64_t, Record*> Dwarf2LMap; 387 for (DwarfRegNumsMapTy::iterator 388 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 389 int DwarfRegNo = I->second[i]; 390 if (DwarfRegNo < 0) 391 continue; 392 Dwarf2LMap[DwarfRegNo] = I->first; 393 } 394 395 for (std::map<uint64_t, Record*>::iterator 396 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I) 397 OS << " { " << I->first << "U, " << getQualifiedName(I->second) 398 << " },\n"; 399 400 OS << "};\n"; 401 } else { 402 OS << ";\n"; 403 } 404 405 // We have to store the size in a const global, it's used in multiple 406 // places. 407 OS << "extern const unsigned " << Namespace 408 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize"; 409 if (!isCtor) 410 OS << " = array_lengthof(" << Namespace 411 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 412 << "Dwarf2L);\n\n"; 413 else 414 OS << ";\n\n"; 415 } 416 } 417 418 for (auto &RE : Regs) { 419 Record *Reg = RE.TheDef; 420 const RecordVal *V = Reg->getValue("DwarfAlias"); 421 if (!V || !V->getValue()) 422 continue; 423 424 DefInit *DI = cast<DefInit>(V->getValue()); 425 Record *Alias = DI->getDef(); 426 DwarfRegNums[Reg] = DwarfRegNums[Alias]; 427 } 428 429 // Emit information about the dwarf register numbers. 430 for (unsigned j = 0; j < 2; ++j) { 431 for (unsigned i = 0, e = maxLength; i != e; ++i) { 432 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 433 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 434 OS << i << "L2Dwarf[]"; 435 if (!isCtor) { 436 OS << " = {\n"; 437 // Store the mapping sorted by the Dwarf reg num so lookup can be done 438 // with a binary search. 439 for (DwarfRegNumsMapTy::iterator 440 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 441 int RegNo = I->second[i]; 442 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 443 continue; 444 445 OS << " { " << getQualifiedName(I->first) << ", " << RegNo 446 << "U },\n"; 447 } 448 OS << "};\n"; 449 } else { 450 OS << ";\n"; 451 } 452 453 // We have to store the size in a const global, it's used in multiple 454 // places. 455 OS << "extern const unsigned " << Namespace 456 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 457 if (!isCtor) 458 OS << " = array_lengthof(" << Namespace 459 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 460 else 461 OS << ";\n\n"; 462 } 463 } 464 } 465 466 void RegisterInfoEmitter::EmitRegMapping( 467 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 468 // Emit the initializer so the tables from EmitRegMappingTables get wired up 469 // to the MCRegisterInfo object. 470 unsigned maxLength = 0; 471 for (auto &RE : Regs) { 472 Record *Reg = RE.TheDef; 473 maxLength = std::max((size_t)maxLength, 474 Reg->getValueAsListOfInts("DwarfNumbers").size()); 475 } 476 477 if (!maxLength) 478 return; 479 480 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 481 482 // Emit reverse information about the dwarf register numbers. 483 for (unsigned j = 0; j < 2; ++j) { 484 OS << " switch ("; 485 if (j == 0) 486 OS << "DwarfFlavour"; 487 else 488 OS << "EHFlavour"; 489 OS << ") {\n" 490 << " default:\n" 491 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 492 493 for (unsigned i = 0, e = maxLength; i != e; ++i) { 494 OS << " case " << i << ":\n"; 495 OS << " "; 496 if (!isCtor) 497 OS << "RI->"; 498 std::string Tmp; 499 raw_string_ostream(Tmp) << Namespace 500 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 501 << "Dwarf2L"; 502 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 503 if (j == 0) 504 OS << "false"; 505 else 506 OS << "true"; 507 OS << ");\n"; 508 OS << " break;\n"; 509 } 510 OS << " }\n"; 511 } 512 513 // Emit information about the dwarf register numbers. 514 for (unsigned j = 0; j < 2; ++j) { 515 OS << " switch ("; 516 if (j == 0) 517 OS << "DwarfFlavour"; 518 else 519 OS << "EHFlavour"; 520 OS << ") {\n" 521 << " default:\n" 522 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 523 524 for (unsigned i = 0, e = maxLength; i != e; ++i) { 525 OS << " case " << i << ":\n"; 526 OS << " "; 527 if (!isCtor) 528 OS << "RI->"; 529 std::string Tmp; 530 raw_string_ostream(Tmp) << Namespace 531 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 532 << "L2Dwarf"; 533 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 534 if (j == 0) 535 OS << "false"; 536 else 537 OS << "true"; 538 OS << ");\n"; 539 OS << " break;\n"; 540 } 541 OS << " }\n"; 542 } 543 } 544 545 // Print a BitVector as a sequence of hex numbers using a little-endian mapping. 546 // Width is the number of bits per hex number. 547 static void printBitVectorAsHex(raw_ostream &OS, 548 const BitVector &Bits, 549 unsigned Width) { 550 assert(Width <= 32 && "Width too large"); 551 unsigned Digits = (Width + 3) / 4; 552 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 553 unsigned Value = 0; 554 for (unsigned j = 0; j != Width && i + j != e; ++j) 555 Value |= Bits.test(i + j) << j; 556 OS << format("0x%0*x, ", Digits, Value); 557 } 558 } 559 560 // Helper to emit a set of bits into a constant byte array. 561 class BitVectorEmitter { 562 BitVector Values; 563 public: 564 void add(unsigned v) { 565 if (v >= Values.size()) 566 Values.resize(((v/8)+1)*8); // Round up to the next byte. 567 Values[v] = true; 568 } 569 570 void print(raw_ostream &OS) { 571 printBitVectorAsHex(OS, Values, 8); 572 } 573 }; 574 575 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 576 OS << getEnumName(VT); 577 } 578 579 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 580 OS << Idx->EnumValue; 581 } 582 583 // Differentially encoded register and regunit lists allow for better 584 // compression on regular register banks. The sequence is computed from the 585 // differential list as: 586 // 587 // out[0] = InitVal; 588 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 589 // 590 // The initial value depends on the specific list. The list is terminated by a 591 // 0 differential which means we can't encode repeated elements. 592 593 typedef SmallVector<uint16_t, 4> DiffVec; 594 typedef SmallVector<LaneBitmask, 4> MaskVec; 595 596 // Differentially encode a sequence of numbers into V. The starting value and 597 // terminating 0 are not added to V, so it will have the same size as List. 598 static 599 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) { 600 assert(V.empty() && "Clear DiffVec before diffEncode."); 601 uint16_t Val = uint16_t(InitVal); 602 603 for (uint16_t Cur : List) { 604 V.push_back(Cur - Val); 605 Val = Cur; 606 } 607 return V; 608 } 609 610 template<typename Iter> 611 static 612 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 613 assert(V.empty() && "Clear DiffVec before diffEncode."); 614 uint16_t Val = uint16_t(InitVal); 615 for (Iter I = Begin; I != End; ++I) { 616 uint16_t Cur = (*I)->EnumValue; 617 V.push_back(Cur - Val); 618 Val = Cur; 619 } 620 return V; 621 } 622 623 static void printDiff16(raw_ostream &OS, uint16_t Val) { 624 OS << Val; 625 } 626 627 static void printMask(raw_ostream &OS, LaneBitmask Val) { 628 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; 629 } 630 631 // Try to combine Idx's compose map into Vec if it is compatible. 632 // Return false if it's not possible. 633 static bool combine(const CodeGenSubRegIndex *Idx, 634 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 635 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 636 for (const auto &I : Map) { 637 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 638 if (Entry && Entry != I.second) 639 return false; 640 } 641 642 // All entries are compatible. Make it so. 643 for (const auto &I : Map) { 644 auto *&Entry = Vec[I.first->EnumValue - 1]; 645 assert((!Entry || Entry == I.second) && 646 "Expected EnumValue to be unique"); 647 Entry = I.second; 648 } 649 return true; 650 } 651 652 void 653 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 654 CodeGenRegBank &RegBank, 655 const std::string &ClName) { 656 const auto &SubRegIndices = RegBank.getSubRegIndices(); 657 OS << "unsigned " << ClName 658 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 659 660 // Many sub-register indexes are composition-compatible, meaning that 661 // 662 // compose(IdxA, IdxB) == compose(IdxA', IdxB) 663 // 664 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 665 // The illegal entries can be use as wildcards to compress the table further. 666 667 // Map each Sub-register index to a compatible table row. 668 SmallVector<unsigned, 4> RowMap; 669 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 670 671 auto SubRegIndicesSize = 672 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 673 for (const auto &Idx : SubRegIndices) { 674 unsigned Found = ~0u; 675 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 676 if (combine(&Idx, Rows[r])) { 677 Found = r; 678 break; 679 } 680 } 681 if (Found == ~0u) { 682 Found = Rows.size(); 683 Rows.resize(Found + 1); 684 Rows.back().resize(SubRegIndicesSize); 685 combine(&Idx, Rows.back()); 686 } 687 RowMap.push_back(Found); 688 } 689 690 // Output the row map if there is multiple rows. 691 if (Rows.size() > 1) { 692 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) 693 << " RowMap[" << SubRegIndicesSize << "] = {\n "; 694 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 695 OS << RowMap[i] << ", "; 696 OS << "\n };\n"; 697 } 698 699 // Output the rows. 700 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 701 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 702 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 703 OS << " { "; 704 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 705 if (Rows[r][i]) 706 OS << Rows[r][i]->EnumValue << ", "; 707 else 708 OS << "0, "; 709 OS << "},\n"; 710 } 711 OS << " };\n\n"; 712 713 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" 714 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 715 if (Rows.size() > 1) 716 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 717 else 718 OS << " return Rows[0][IdxB];\n"; 719 OS << "}\n\n"; 720 } 721 722 void 723 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 724 CodeGenRegBank &RegBank, 725 const std::string &ClName) { 726 // See the comments in computeSubRegLaneMasks() for our goal here. 727 const auto &SubRegIndices = RegBank.getSubRegIndices(); 728 729 // Create a list of Mask+Rotate operations, with equivalent entries merged. 730 SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 731 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 732 for (const auto &Idx : SubRegIndices) { 733 const SmallVector<MaskRolPair, 1> &IdxSequence 734 = Idx.CompositionLaneMaskTransform; 735 736 unsigned Found = ~0u; 737 unsigned SIdx = 0; 738 unsigned NextSIdx; 739 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 740 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 741 NextSIdx = SIdx + Sequence.size() + 1; 742 if (Sequence == IdxSequence) { 743 Found = SIdx; 744 break; 745 } 746 } 747 if (Found == ~0u) { 748 Sequences.push_back(IdxSequence); 749 Found = SIdx; 750 } 751 SubReg2SequenceIndexMap.push_back(Found); 752 } 753 754 OS << " struct MaskRolOp {\n" 755 " LaneBitmask Mask;\n" 756 " uint8_t RotateLeft;\n" 757 " };\n" 758 " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 759 unsigned Idx = 0; 760 for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 761 OS << " "; 762 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 763 for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) { 764 const MaskRolPair &P = Sequence[p]; 765 printMask(OS << "{ ", P.Mask); 766 OS << format(", %2u }, ", P.RotateLeft); 767 } 768 OS << "{ LaneBitmask::getNone(), 0 }"; 769 if (s+1 != se) 770 OS << ", "; 771 OS << " // Sequence " << Idx << "\n"; 772 Idx += Sequence.size() + 1; 773 } 774 OS << " };\n" 775 " static const MaskRolOp *const CompositeSequences[] = {\n"; 776 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 777 OS << " "; 778 unsigned Idx = SubReg2SequenceIndexMap[i]; 779 OS << format("&LaneMaskComposeSequences[%u]", Idx); 780 if (i+1 != e) 781 OS << ","; 782 OS << " // to " << SubRegIndices[i].getName() << "\n"; 783 } 784 OS << " };\n\n"; 785 786 OS << "LaneBitmask " << ClName 787 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 788 " const {\n" 789 " --IdxA; assert(IdxA < " << SubRegIndices.size() 790 << " && \"Subregister index out of bounds\");\n" 791 " LaneBitmask Result;\n" 792 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 793 " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n" 794 " if (unsigned S = Ops->RotateLeft)\n" 795 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n" 796 " else\n" 797 " Result |= LaneBitmask(M);\n" 798 " }\n" 799 " return Result;\n" 800 "}\n\n"; 801 802 OS << "LaneBitmask " << ClName 803 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 804 " LaneBitmask LaneMask) const {\n" 805 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 806 " --IdxA; assert(IdxA < " << SubRegIndices.size() 807 << " && \"Subregister index out of bounds\");\n" 808 " LaneBitmask Result;\n" 809 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 810 " LaneBitmask::Type M = LaneMask.getAsInteger();\n" 811 " if (unsigned S = Ops->RotateLeft)\n" 812 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n" 813 " else\n" 814 " Result |= LaneBitmask(M);\n" 815 " }\n" 816 " return Result;\n" 817 "}\n\n"; 818 } 819 820 // 821 // runMCDesc - Print out MC register descriptions. 822 // 823 void 824 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 825 CodeGenRegBank &RegBank) { 826 emitSourceFileHeader("MC Register Information", OS); 827 828 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 829 OS << "#undef GET_REGINFO_MC_DESC\n\n"; 830 831 const auto &Regs = RegBank.getRegisters(); 832 833 auto &SubRegIndices = RegBank.getSubRegIndices(); 834 // The lists of sub-registers and super-registers go in the same array. That 835 // allows us to share suffixes. 836 typedef std::vector<const CodeGenRegister*> RegVec; 837 838 // Differentially encoded lists. 839 SequenceToOffsetTable<DiffVec> DiffSeqs; 840 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 841 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 842 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 843 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 844 845 // List of lane masks accompanying register unit sequences. 846 SequenceToOffsetTable<MaskVec> LaneMaskSeqs; 847 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 848 849 // Keep track of sub-register names as well. These are not differentially 850 // encoded. 851 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 852 SequenceToOffsetTable<SubRegIdxVec, deref<llvm::less>> SubRegIdxSeqs; 853 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 854 855 SequenceToOffsetTable<std::string> RegStrings; 856 857 // Precompute register lists for the SequenceToOffsetTable. 858 unsigned i = 0; 859 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 860 const auto &Reg = *I; 861 RegStrings.add(Reg.getName()); 862 863 // Compute the ordered sub-register list. 864 SetVector<const CodeGenRegister*> SR; 865 Reg.addSubRegsPreOrder(SR, RegBank); 866 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 867 DiffSeqs.add(SubRegLists[i]); 868 869 // Compute the corresponding sub-register indexes. 870 SubRegIdxVec &SRIs = SubRegIdxLists[i]; 871 for (const CodeGenRegister *S : SR) 872 SRIs.push_back(Reg.getSubRegIndex(S)); 873 SubRegIdxSeqs.add(SRIs); 874 875 // Super-registers are already computed. 876 const RegVec &SuperRegList = Reg.getSuperRegs(); 877 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 878 SuperRegList.end()); 879 DiffSeqs.add(SuperRegLists[i]); 880 881 // Differentially encode the register unit list, seeded by register number. 882 // First compute a scale factor that allows more diff-lists to be reused: 883 // 884 // D0 -> (S0, S1) 885 // D1 -> (S2, S3) 886 // 887 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 888 // value for the differential decoder is the register number multiplied by 889 // the scale. 890 // 891 // Check the neighboring registers for arithmetic progressions. 892 unsigned ScaleA = ~0u, ScaleB = ~0u; 893 SparseBitVector<> RUs = Reg.getNativeRegUnits(); 894 if (I != Regs.begin() && 895 std::prev(I)->getNativeRegUnits().count() == RUs.count()) 896 ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin(); 897 if (std::next(I) != Regs.end() && 898 std::next(I)->getNativeRegUnits().count() == RUs.count()) 899 ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin(); 900 unsigned Scale = std::min(ScaleB, ScaleA); 901 // Default the scale to 0 if it can't be encoded in 4 bits. 902 if (Scale >= 16) 903 Scale = 0; 904 RegUnitInitScale[i] = Scale; 905 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); 906 907 const auto &RUMasks = Reg.getRegUnitLaneMasks(); 908 MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 909 assert(LaneMaskVec.empty()); 910 LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end()); 911 // Terminator mask should not be used inside of the list. 912 #ifndef NDEBUG 913 for (LaneBitmask M : LaneMaskVec) { 914 assert(!M.all() && "terminator mask should not be part of the list"); 915 } 916 #endif 917 LaneMaskSeqs.add(LaneMaskVec); 918 } 919 920 // Compute the final layout of the sequence table. 921 DiffSeqs.layout(); 922 LaneMaskSeqs.layout(); 923 SubRegIdxSeqs.layout(); 924 925 OS << "namespace llvm {\n\n"; 926 927 const std::string &TargetName = Target.getName(); 928 929 // Emit the shared table of differential lists. 930 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 931 DiffSeqs.emit(OS, printDiff16); 932 OS << "};\n\n"; 933 934 // Emit the shared table of regunit lane mask sequences. 935 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 936 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); 937 OS << "};\n\n"; 938 939 // Emit the table of sub-register indexes. 940 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 941 SubRegIdxSeqs.emit(OS, printSubRegIndex); 942 OS << "};\n\n"; 943 944 // Emit the table of sub-register index sizes. 945 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 946 << TargetName << "SubRegIdxRanges[] = {\n"; 947 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 948 for (const auto &Idx : SubRegIndices) { 949 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " 950 << Idx.getName() << "\n"; 951 } 952 OS << "};\n\n"; 953 954 // Emit the string table. 955 RegStrings.layout(); 956 OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 957 RegStrings.emit(OS, printChar); 958 OS << "};\n\n"; 959 960 OS << "extern const MCRegisterDesc " << TargetName 961 << "RegDesc[] = { // Descriptors\n"; 962 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 963 964 // Emit the register descriptors now. 965 i = 0; 966 for (const auto &Reg : Regs) { 967 OS << " { " << RegStrings.get(Reg.getName()) << ", " 968 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 969 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 970 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " 971 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n"; 972 ++i; 973 } 974 OS << "};\n\n"; // End of register descriptors... 975 976 // Emit the table of register unit roots. Each regunit has one or two root 977 // registers. 978 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 979 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 980 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 981 assert(!Roots.empty() && "All regunits must have a root register."); 982 assert(Roots.size() <= 2 && "More than two roots not supported yet."); 983 OS << " { " << getQualifiedName(Roots.front()->TheDef); 984 for (unsigned r = 1; r != Roots.size(); ++r) 985 OS << ", " << getQualifiedName(Roots[r]->TheDef); 986 OS << " },\n"; 987 } 988 OS << "};\n\n"; 989 990 const auto &RegisterClasses = RegBank.getRegClasses(); 991 992 // Loop over all of the register classes... emitting each one. 993 OS << "namespace { // Register classes...\n"; 994 995 SequenceToOffsetTable<std::string> RegClassStrings; 996 997 // Emit the register enum value arrays for each RegisterClass 998 for (const auto &RC : RegisterClasses) { 999 ArrayRef<Record*> Order = RC.getOrder(); 1000 1001 // Give the register class a legal C name if it's anonymous. 1002 const std::string &Name = RC.getName(); 1003 1004 RegClassStrings.add(Name); 1005 1006 // Emit the register list now. 1007 OS << " // " << Name << " Register Class...\n" 1008 << " const MCPhysReg " << Name 1009 << "[] = {\n "; 1010 for (Record *Reg : Order) { 1011 OS << getQualifiedName(Reg) << ", "; 1012 } 1013 OS << "\n };\n\n"; 1014 1015 OS << " // " << Name << " Bit set.\n" 1016 << " const uint8_t " << Name 1017 << "Bits[] = {\n "; 1018 BitVectorEmitter BVE; 1019 for (Record *Reg : Order) { 1020 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 1021 } 1022 BVE.print(OS); 1023 OS << "\n };\n\n"; 1024 1025 } 1026 OS << "} // end anonymous namespace\n\n"; 1027 1028 RegClassStrings.layout(); 1029 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; 1030 RegClassStrings.emit(OS, printChar); 1031 OS << "};\n\n"; 1032 1033 OS << "extern const MCRegisterClass " << TargetName 1034 << "MCRegisterClasses[] = {\n"; 1035 1036 for (const auto &RC : RegisterClasses) { 1037 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); 1038 uint32_t RegSize = 0; 1039 if (RC.RSI.isSimple()) 1040 RegSize = RC.RSI.getSimple().RegSize; 1041 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " 1042 << RegClassStrings.get(RC.getName()) << ", " 1043 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 1044 << RC.getQualifiedName() + "RegClassID" << ", " 1045 << RegSize/8 << ", " 1046 << RC.CopyCost << ", " 1047 << ( RC.Allocatable ? "true" : "false" ) << " },\n"; 1048 } 1049 1050 OS << "};\n\n"; 1051 1052 EmitRegMappingTables(OS, Regs, false); 1053 1054 // Emit Reg encoding table 1055 OS << "extern const uint16_t " << TargetName; 1056 OS << "RegEncodingTable[] = {\n"; 1057 // Add entry for NoRegister 1058 OS << " 0,\n"; 1059 for (const auto &RE : Regs) { 1060 Record *Reg = RE.TheDef; 1061 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1062 uint64_t Value = 0; 1063 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1064 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1065 Value |= (uint64_t)B->getValue() << b; 1066 } 1067 OS << " " << Value << ",\n"; 1068 } 1069 OS << "};\n"; // End of HW encoding table 1070 1071 // MCRegisterInfo initialization routine. 1072 OS << "static inline void Init" << TargetName 1073 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1074 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1075 "{\n" 1076 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1077 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1078 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1079 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1080 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1081 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1082 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1083 << TargetName << "SubRegIdxRanges, " << TargetName 1084 << "RegEncodingTable);\n\n"; 1085 1086 EmitRegMapping(OS, Regs, false); 1087 1088 OS << "}\n\n"; 1089 1090 OS << "} // end namespace llvm\n\n"; 1091 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1092 } 1093 1094 void 1095 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 1096 CodeGenRegBank &RegBank) { 1097 emitSourceFileHeader("Register Information Header Fragment", OS); 1098 1099 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1100 OS << "#undef GET_REGINFO_HEADER\n\n"; 1101 1102 const std::string &TargetName = Target.getName(); 1103 std::string ClassName = TargetName + "GenRegisterInfo"; 1104 1105 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; 1106 1107 OS << "namespace llvm {\n\n"; 1108 1109 OS << "class " << TargetName << "FrameLowering;\n\n"; 1110 1111 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1112 << " explicit " << ClassName 1113 << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n" 1114 << " unsigned PC = 0, unsigned HwMode = 0);\n"; 1115 if (!RegBank.getSubRegIndices().empty()) { 1116 OS << " unsigned composeSubRegIndicesImpl" 1117 << "(unsigned, unsigned) const override;\n" 1118 << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1119 << "(unsigned, LaneBitmask) const override;\n" 1120 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1121 << "(unsigned, LaneBitmask) const override;\n" 1122 << " const TargetRegisterClass *getSubClassWithSubReg" 1123 << "(const TargetRegisterClass*, unsigned) const override;\n"; 1124 } 1125 OS << " const RegClassWeight &getRegClassWeight(" 1126 << "const TargetRegisterClass *RC) const override;\n" 1127 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1128 << " unsigned getNumRegPressureSets() const override;\n" 1129 << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1130 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1131 "Idx) const override;\n" 1132 << " const int *getRegClassPressureSets(" 1133 << "const TargetRegisterClass *RC) const override;\n" 1134 << " const int *getRegUnitPressureSets(" 1135 << "unsigned RegUnit) const override;\n" 1136 << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1137 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1138 << " /// Devirtualized TargetFrameLowering.\n" 1139 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1140 << " const MachineFunction &MF);\n" 1141 << "};\n\n"; 1142 1143 const auto &RegisterClasses = RegBank.getRegClasses(); 1144 1145 if (!RegisterClasses.empty()) { 1146 OS << "namespace " << RegisterClasses.front().Namespace 1147 << " { // Register classes\n"; 1148 1149 for (const auto &RC : RegisterClasses) { 1150 const std::string &Name = RC.getName(); 1151 1152 // Output the extern for the instance. 1153 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1154 } 1155 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1156 } 1157 OS << "} // end namespace llvm\n\n"; 1158 OS << "#endif // GET_REGINFO_HEADER\n\n"; 1159 } 1160 1161 // 1162 // runTargetDesc - Output the target register and register file descriptions. 1163 // 1164 void 1165 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1166 CodeGenRegBank &RegBank){ 1167 emitSourceFileHeader("Target Register and Register Classes Information", OS); 1168 1169 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1170 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1171 1172 OS << "namespace llvm {\n\n"; 1173 1174 // Get access to MCRegisterClass data. 1175 OS << "extern const MCRegisterClass " << Target.getName() 1176 << "MCRegisterClasses[];\n"; 1177 1178 // Start out by emitting each of the register classes. 1179 const auto &RegisterClasses = RegBank.getRegClasses(); 1180 const auto &SubRegIndices = RegBank.getSubRegIndices(); 1181 1182 // Collect all registers belonging to any allocatable class. 1183 std::set<Record*> AllocatableRegs; 1184 1185 // Collect allocatable registers. 1186 for (const auto &RC : RegisterClasses) { 1187 ArrayRef<Record*> Order = RC.getOrder(); 1188 1189 if (RC.Allocatable) 1190 AllocatableRegs.insert(Order.begin(), Order.end()); 1191 } 1192 1193 const CodeGenHwModes &CGH = Target.getHwModes(); 1194 unsigned NumModes = CGH.getNumModeIds(); 1195 1196 // Build a shared array of value types. 1197 SequenceToOffsetTable<std::vector<MVT::SimpleValueType>> VTSeqs; 1198 for (unsigned M = 0; M < NumModes; ++M) { 1199 for (const auto &RC : RegisterClasses) { 1200 std::vector<MVT::SimpleValueType> S; 1201 for (const ValueTypeByHwMode &VVT : RC.VTs) 1202 S.push_back(VVT.get(M).SimpleTy); 1203 VTSeqs.add(S); 1204 } 1205 } 1206 VTSeqs.layout(); 1207 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1208 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1209 OS << "};\n"; 1210 1211 // Emit SubRegIndex names, skipping 0. 1212 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1213 1214 for (const auto &Idx : SubRegIndices) { 1215 OS << Idx.getName(); 1216 OS << "\", \""; 1217 } 1218 OS << "\" };\n\n"; 1219 1220 // Emit SubRegIndex lane masks, including 0. 1221 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1222 "LaneBitmask::getAll(),\n"; 1223 for (const auto &Idx : SubRegIndices) { 1224 printMask(OS << " ", Idx.LaneMask); 1225 OS << ", // " << Idx.getName() << '\n'; 1226 } 1227 OS << " };\n\n"; 1228 1229 OS << "\n"; 1230 1231 // Now that all of the structs have been emitted, emit the instances. 1232 if (!RegisterClasses.empty()) { 1233 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1234 << " = {\n"; 1235 for (unsigned M = 0; M < NumModes; ++M) { 1236 unsigned EV = 0; 1237 OS << " // Mode = " << M << " ("; 1238 if (M == 0) 1239 OS << "Default"; 1240 else 1241 OS << CGH.getMode(M).Name; 1242 OS << ")\n"; 1243 for (const auto &RC : RegisterClasses) { 1244 assert(RC.EnumValue == EV++ && "Unexpected order of register classes"); 1245 (void)EV; 1246 const RegSizeInfo &RI = RC.RSI.get(M); 1247 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1248 << RI.SpillAlignment; 1249 std::vector<MVT::SimpleValueType> VTs; 1250 for (const ValueTypeByHwMode &VVT : RC.VTs) 1251 VTs.push_back(VVT.get(M).SimpleTy); 1252 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " 1253 << RC.getName() << '\n'; 1254 } 1255 } 1256 OS << "};\n"; 1257 1258 1259 OS << "\nstatic const TargetRegisterClass *const " 1260 << "NullRegClasses[] = { nullptr };\n\n"; 1261 1262 // Emit register class bit mask tables. The first bit mask emitted for a 1263 // register class, RC, is the set of sub-classes, including RC itself. 1264 // 1265 // If RC has super-registers, also create a list of subreg indices and bit 1266 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1267 // SuperRC, that satisfies: 1268 // 1269 // For all SuperReg in SuperRC: SuperReg:Idx in RC 1270 // 1271 // The 0-terminated list of subreg indices starts at: 1272 // 1273 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1274 // 1275 // The corresponding bitmasks follow the sub-class mask in memory. Each 1276 // mask has RCMaskWords uint32_t entries. 1277 // 1278 // Every bit mask present in the list has at least one bit set. 1279 1280 // Compress the sub-reg index lists. 1281 typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1282 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1283 SequenceToOffsetTable<IdxList, deref<llvm::less>> SuperRegIdxSeqs; 1284 BitVector MaskBV(RegisterClasses.size()); 1285 1286 for (const auto &RC : RegisterClasses) { 1287 OS << "static const uint32_t " << RC.getName() 1288 << "SubClassMask[] = {\n "; 1289 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1290 1291 // Emit super-reg class masks for any relevant SubRegIndices that can 1292 // project into RC. 1293 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1294 for (auto &Idx : SubRegIndices) { 1295 MaskBV.reset(); 1296 RC.getSuperRegClasses(&Idx, MaskBV); 1297 if (MaskBV.none()) 1298 continue; 1299 SRIList.push_back(&Idx); 1300 OS << "\n "; 1301 printBitVectorAsHex(OS, MaskBV, 32); 1302 OS << "// " << Idx.getName(); 1303 } 1304 SuperRegIdxSeqs.add(SRIList); 1305 OS << "\n};\n\n"; 1306 } 1307 1308 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1309 SuperRegIdxSeqs.layout(); 1310 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1311 OS << "};\n\n"; 1312 1313 // Emit NULL terminated super-class lists. 1314 for (const auto &RC : RegisterClasses) { 1315 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1316 1317 // Skip classes without supers. We can reuse NullRegClasses. 1318 if (Supers.empty()) 1319 continue; 1320 1321 OS << "static const TargetRegisterClass *const " 1322 << RC.getName() << "Superclasses[] = {\n"; 1323 for (const auto *Super : Supers) 1324 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; 1325 OS << " nullptr\n};\n\n"; 1326 } 1327 1328 // Emit methods. 1329 for (const auto &RC : RegisterClasses) { 1330 if (!RC.AltOrderSelect.empty()) { 1331 OS << "\nstatic inline unsigned " << RC.getName() 1332 << "AltOrderSelect(const MachineFunction &MF) {" 1333 << RC.AltOrderSelect << "}\n\n" 1334 << "static ArrayRef<MCPhysReg> " << RC.getName() 1335 << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1336 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1337 ArrayRef<Record*> Elems = RC.getOrder(oi); 1338 if (!Elems.empty()) { 1339 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1340 for (unsigned elem = 0; elem != Elems.size(); ++elem) 1341 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1342 OS << " };\n"; 1343 } 1344 } 1345 OS << " const MCRegisterClass &MCR = " << Target.getName() 1346 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1347 << " const ArrayRef<MCPhysReg> Order[] = {\n" 1348 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1349 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1350 if (RC.getOrder(oi).empty()) 1351 OS << "),\n ArrayRef<MCPhysReg>("; 1352 else 1353 OS << "),\n makeArrayRef(AltOrder" << oi; 1354 OS << ")\n };\n const unsigned Select = " << RC.getName() 1355 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1356 << ");\n return Order[Select];\n}\n"; 1357 } 1358 } 1359 1360 // Now emit the actual value-initialized register class instances. 1361 OS << "\nnamespace " << RegisterClasses.front().Namespace 1362 << " { // Register class instances\n"; 1363 1364 for (const auto &RC : RegisterClasses) { 1365 OS << " extern const TargetRegisterClass " << RC.getName() 1366 << "RegClass = {\n " << '&' << Target.getName() 1367 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1368 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1369 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; 1370 printMask(OS, RC.LaneMask); 1371 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1372 << (RC.HasDisjunctSubRegs?"true":"false") 1373 << ", /* HasDisjunctSubRegs */\n " 1374 << (RC.CoveredBySubRegs?"true":"false") 1375 << ", /* CoveredBySubRegs */\n "; 1376 if (RC.getSuperClasses().empty()) 1377 OS << "NullRegClasses,\n "; 1378 else 1379 OS << RC.getName() << "Superclasses,\n "; 1380 if (RC.AltOrderSelect.empty()) 1381 OS << "nullptr\n"; 1382 else 1383 OS << RC.getName() << "GetRawAllocationOrder\n"; 1384 OS << " };\n\n"; 1385 } 1386 1387 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1388 } 1389 1390 OS << "\nnamespace {\n"; 1391 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1392 for (const auto &RC : RegisterClasses) 1393 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1394 OS << " };\n"; 1395 OS << "} // end anonymous namespace\n"; 1396 1397 // Emit extra information about registers. 1398 const std::string &TargetName = Target.getName(); 1399 OS << "\nstatic const TargetRegisterInfoDesc " 1400 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; 1401 OS << " { 0, false },\n"; 1402 1403 const auto &Regs = RegBank.getRegisters(); 1404 for (const auto &Reg : Regs) { 1405 OS << " { "; 1406 OS << Reg.CostPerUse << ", " 1407 << ( AllocatableRegs.count(Reg.TheDef) != 0 ? "true" : "false" ) 1408 << " },\n"; 1409 } 1410 OS << "};\n"; // End of register descriptors... 1411 1412 1413 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; 1414 1415 auto SubRegIndicesSize = 1416 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1417 1418 if (!SubRegIndices.empty()) { 1419 emitComposeSubRegIndices(OS, RegBank, ClassName); 1420 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); 1421 } 1422 1423 // Emit getSubClassWithSubReg. 1424 if (!SubRegIndices.empty()) { 1425 OS << "const TargetRegisterClass *" << ClassName 1426 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1427 << " const {\n"; 1428 // Use the smallest type that can hold a regclass ID with room for a 1429 // sentinel. 1430 if (RegisterClasses.size() < UINT8_MAX) 1431 OS << " static const uint8_t Table["; 1432 else if (RegisterClasses.size() < UINT16_MAX) 1433 OS << " static const uint16_t Table["; 1434 else 1435 PrintFatalError("Too many register classes."); 1436 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1437 for (const auto &RC : RegisterClasses) { 1438 OS << " {\t// " << RC.getName() << "\n"; 1439 for (auto &Idx : SubRegIndices) { 1440 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1441 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1442 << " -> " << SRC->getName() << "\n"; 1443 else 1444 OS << " 0,\t// " << Idx.getName() << "\n"; 1445 } 1446 OS << " },\n"; 1447 } 1448 OS << " };\n assert(RC && \"Missing regclass\");\n" 1449 << " if (!Idx) return RC;\n --Idx;\n" 1450 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1451 << " unsigned TV = Table[RC->getID()][Idx];\n" 1452 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1453 } 1454 1455 EmitRegUnitPressure(OS, RegBank, ClassName); 1456 1457 // Emit the constructor of the class... 1458 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1459 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1460 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1461 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1462 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1463 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1464 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1465 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1466 << TargetName << "SubRegIdxRanges[];\n"; 1467 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1468 1469 EmitRegMappingTables(OS, Regs, true); 1470 1471 OS << ClassName << "::\n" << ClassName 1472 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n" 1473 " unsigned PC, unsigned HwMode)\n" 1474 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 1475 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n" 1476 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable,\n" 1477 << " "; 1478 printMask(OS, RegBank.CoveringLanes); 1479 OS << ", RegClassInfos, HwMode) {\n" 1480 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1481 << ", RA, PC,\n " << TargetName 1482 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1483 << " " << TargetName << "RegUnitRoots,\n" 1484 << " " << RegBank.getNumNativeRegUnits() << ",\n" 1485 << " " << TargetName << "RegDiffLists,\n" 1486 << " " << TargetName << "LaneMaskLists,\n" 1487 << " " << TargetName << "RegStrings,\n" 1488 << " " << TargetName << "RegClassStrings,\n" 1489 << " " << TargetName << "SubRegIdxLists,\n" 1490 << " " << SubRegIndicesSize + 1 << ",\n" 1491 << " " << TargetName << "SubRegIdxRanges,\n" 1492 << " " << TargetName << "RegEncodingTable);\n\n"; 1493 1494 EmitRegMapping(OS, Regs, true); 1495 1496 OS << "}\n\n"; 1497 1498 // Emit CalleeSavedRegs information. 1499 std::vector<Record*> CSRSets = 1500 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1501 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1502 Record *CSRSet = CSRSets[i]; 1503 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1504 assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1505 1506 // Emit the *_SaveList list of callee-saved registers. 1507 OS << "static const MCPhysReg " << CSRSet->getName() 1508 << "_SaveList[] = { "; 1509 for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1510 OS << getQualifiedName((*Regs)[r]) << ", "; 1511 OS << "0 };\n"; 1512 1513 // Emit the *_RegMask bit mask of call-preserved registers. 1514 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1515 1516 // Check for an optional OtherPreserved set. 1517 // Add those registers to RegMask, but not to SaveList. 1518 if (DagInit *OPDag = 1519 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1520 SetTheory::RecSet OPSet; 1521 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1522 Covered |= RegBank.computeCoveredRegisters( 1523 ArrayRef<Record*>(OPSet.begin(), OPSet.end())); 1524 } 1525 1526 OS << "static const uint32_t " << CSRSet->getName() 1527 << "_RegMask[] = { "; 1528 printBitVectorAsHex(OS, Covered, 32); 1529 OS << "};\n"; 1530 } 1531 OS << "\n\n"; 1532 1533 OS << "ArrayRef<const uint32_t *> " << ClassName 1534 << "::getRegMasks() const {\n"; 1535 if (!CSRSets.empty()) { 1536 OS << " static const uint32_t *const Masks[] = {\n"; 1537 for (Record *CSRSet : CSRSets) 1538 OS << " " << CSRSet->getName() << "_RegMask,\n"; 1539 OS << " };\n"; 1540 OS << " return makeArrayRef(Masks);\n"; 1541 } else { 1542 OS << " return None;\n"; 1543 } 1544 OS << "}\n\n"; 1545 1546 OS << "ArrayRef<const char *> " << ClassName 1547 << "::getRegMaskNames() const {\n"; 1548 if (!CSRSets.empty()) { 1549 OS << " static const char *const Names[] = {\n"; 1550 for (Record *CSRSet : CSRSets) 1551 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1552 OS << " };\n"; 1553 OS << " return makeArrayRef(Names);\n"; 1554 } else { 1555 OS << " return None;\n"; 1556 } 1557 OS << "}\n\n"; 1558 1559 OS << "const " << TargetName << "FrameLowering *\n" << TargetName 1560 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1561 << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1562 << " MF.getSubtarget().getFrameLowering());\n" 1563 << "}\n\n"; 1564 1565 OS << "} // end namespace llvm\n\n"; 1566 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1567 } 1568 1569 void RegisterInfoEmitter::run(raw_ostream &OS) { 1570 CodeGenRegBank &RegBank = Target.getRegBank(); 1571 runEnums(OS, Target, RegBank); 1572 runMCDesc(OS, Target, RegBank); 1573 runTargetHeader(OS, Target, RegBank); 1574 runTargetDesc(OS, Target, RegBank); 1575 1576 if (RegisterInfoDebug) 1577 debugDump(errs()); 1578 } 1579 1580 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { 1581 CodeGenRegBank &RegBank = Target.getRegBank(); 1582 const CodeGenHwModes &CGH = Target.getHwModes(); 1583 unsigned NumModes = CGH.getNumModeIds(); 1584 auto getModeName = [CGH] (unsigned M) -> StringRef { 1585 if (M == 0) 1586 return "Default"; 1587 return CGH.getMode(M).Name; 1588 }; 1589 1590 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { 1591 OS << "RegisterClass " << RC.getName() << ":\n"; 1592 OS << "\tSpillSize: {"; 1593 for (unsigned M = 0; M != NumModes; ++M) 1594 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; 1595 OS << " }\n\tSpillAlignment: {"; 1596 for (unsigned M = 0; M != NumModes; ++M) 1597 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; 1598 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; 1599 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; 1600 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; 1601 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; 1602 OS << "\tRegs:"; 1603 for (const CodeGenRegister *R : RC.getMembers()) { 1604 OS << " " << R->getName(); 1605 } 1606 OS << '\n'; 1607 OS << "\tSubClasses:"; 1608 const BitVector &SubClasses = RC.getSubClasses(); 1609 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { 1610 if (!SubClasses.test(SRC.EnumValue)) 1611 continue; 1612 OS << " " << SRC.getName(); 1613 } 1614 OS << '\n'; 1615 OS << "\tSuperClasses:"; 1616 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { 1617 OS << " " << SRC->getName(); 1618 } 1619 OS << '\n'; 1620 } 1621 1622 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { 1623 OS << "SubRegIndex " << SRI.getName() << ":\n"; 1624 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; 1625 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; 1626 } 1627 1628 for (const CodeGenRegister &R : RegBank.getRegisters()) { 1629 OS << "Register " << R.getName() << ":\n"; 1630 OS << "\tCostPerUse: " << R.CostPerUse << '\n'; 1631 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; 1632 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; 1633 for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { 1634 OS << "\tSubReg " << P.first->getName() 1635 << " = " << P.second->getName() << '\n'; 1636 } 1637 } 1638 } 1639 1640 namespace llvm { 1641 1642 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1643 RegisterInfoEmitter(RK).run(OS); 1644 } 1645 1646 } // end namespace llvm 1647