| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| RegisterBank.h | 95 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
96 RegBank.print(OS);
|
| RegisterBankInfo.h | 54 const RegisterBank *RegBank;
60 const RegisterBank &RegBank)
61 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
73 /// Check that the Mask is compatible with the RegBank.
74 /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
166 /// This element will map to \p RegBank and fully define a mask, whose
169 const RegisterBank &RegBank);
363 /// Record \p RegBank as the register bank that covers \p SVT.
368 /// getRegBankForType(SVT) == &RegBank
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| RegisterBank.h | 93 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
94 RegBank.print(OS);
|
| RegisterBankInfo.h | 59 const RegisterBank *RegBank;
65 const RegisterBank &RegBank)
66 : StartIdx(StartIdx), Length(Length), RegBank(&RegBank) {}
78 /// Check that the Mask is compatible with the RegBank.
79 /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
461 const RegisterBank &RegBank) const;
469 const RegisterBank &RegBank) const;
593 /// \note The mapping RC -> RegBank could be built while adding the
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 77 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
79 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
81 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
190 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
192 unsigned NumRCs = RegBank.getRegClasses().size();
193 unsigned NumSets = RegBank.getNumRegPressureSets();
199 for (const auto &RC : RegBank.getRegClasses()) {
206 OS << " {" << (*Regs.begin())->getWeight(RegBank)
207 << ", " << RegBank.getRegUnitSetWeight(RegUnits);
218 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits()
[all...] |
| CodeGenRegisters.cpp | 56 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
65 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
66 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
80 IdxParts.push_back(RegBank.getSubRegIdx(Parts[i]));
81 RegBank.addConcatSubRegIndex(IdxParts, this);
117 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
126 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i]));
127 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
202 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
[all...] |
| CodeGenTarget.h | 70 mutable std::unique_ptr<CodeGenRegBank> RegBank;
|
| CodeGenTarget.cpp | 222 if (!RegBank)
223 RegBank = llvm::make_unique<CodeGenRegBank>(Records);
224 return *RegBank;
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| CodeGenRegisters.h | 174 // This is valid after computeSubRegs visits all registers during RegBank
189 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
224 bool inheritRegUnits(CodeGenRegBank &RegBank);
231 unsigned getWeight(const CodeGenRegBank &RegBank) const;
|
| /external/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBankInfo.cpp | 48 const RegisterBank &RegBank = getRegBank(Idx);
49 assert(Idx == RegBank.getID() &&
51 dbgs() << "Verify " << RegBank << '\n';
52 assert(RegBank.verify(TRI) && "RegBank is invalid");
60 RegisterBank &RegBank = getRegBank(ID);
61 assert(RegBank.getID() == RegisterBank::InvalidID &&
63 RegBank.ID = ID;
64 RegBank.Name = Name;
195 const RegisterBank &RegBank = getRegBankFromRegClass(*RC)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 63 CodeGenRegBank &RegBank = Target.getRegBank();
64 RegBank.computeDerivedInfo();
92 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
94 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
96 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
195 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
197 unsigned NumRCs = RegBank.getRegClasses().size();
198 unsigned NumSets = RegBank.getNumRegPressureSets();
204 for (const auto &RC : RegBank.getRegClasses()) {
210 RC.buildRegUnitSet(RegBank, RegUnits)
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| CodeGenRegisters.cpp | 76 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
85 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
86 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
100 IdxParts.push_back(RegBank.getSubRegIdx(Part));
168 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
177 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i]));
178 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
193 CodeGenRegister *Reg = RegBank.getReg(Alias);
255 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
267 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
[all...] |
| CodeGenRegisters.h | 200 // This is valid after computeSubRegs visits all registers during RegBank
215 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
250 bool inheritRegUnits(CodeGenRegBank &RegBank);
257 unsigned getWeight(const CodeGenRegBank &RegBank) const;
389 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
437 void buildRegUnitSet(const CodeGenRegBank &RegBank,
|
| CodeGenTarget.h | 54 mutable std::unique_ptr<CodeGenRegBank> RegBank;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBankInfo.cpp | 73 const RegisterBank &RegBank = getRegBank(Idx);
74 assert(Idx == RegBank.getID() &&
76 LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n');
77 assert(RegBank.verify(TRI) && "RegBank is invalid");
121 const RegisterBank &RegBank = getRegBankFromRegClass(*RC);
123 assert(RegBank.covers(*RC) &&
125 return &RegBank;
234 const RegisterBank *RegBank) {
235 return hash_combine(StartIdx, Length, RegBank ? RegBank->getID() : 0)
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 243 CodeGenRegBank &RegBank) {
250 RegBank.computeOverlaps(Overlaps);
262 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
333 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
407 CodeGenRegBank &RegBank) {
433 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
440 for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
448 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
483 CodeGenRegBank &RegBank){
496 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses()
[all...] |
| CodeGenRegisters.cpp | 49 CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
63 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
75 CodeGenRegister *SR = RegBank.getReg(SubList[i]);
76 const SubRegMap &Map = SR->getSubRegs(RegBank);
115 const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
138 SubRegs[RegBank.getCompositeSubRegIndex(O.First, O.Second, true)] =
258 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
277 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
284 Members.insert(RegBank.getReg((*Elements)[i]));
290 RegBank.getSets().evaluate(AltOrders->getElement(i), Order)
[all...] |
| CodeGenTarget.cpp | 113 : Records(records), RegBank(0) {
162 if (!RegBank)
163 RegBank = new CodeGenRegBank(Records);
164 return *RegBank;
|
| CodeGenTarget.h | 68 mutable CodeGenRegBank *RegBank;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/MIRParser/ |
| MIParser.h | 35 UNKNOWN, NORMAL, GENERIC, REGBANK
40 const RegisterBank *RegBank;
|
| MIRParser.cpp | 449 Info.D.RegBank = nullptr;
456 const RegisterBank *RegBank = getRegBank(MF, VReg.Class.Value);
457 if (!RegBank)
462 Info.Kind = VRegInfo::REGBANK;
463 Info.D.RegBank = RegBank;
531 case VRegInfo::REGBANK:
532 MRI.setRegBank(Reg, *Info.D.RegBank);
865 const auto &RegBank = RBI->getRegBank(I);
867 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank))
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMInstructionSelector.cpp | 124 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
125 assert(RegBank && "Can't get reg bank for virtual register");
128 assert((RegBank->getID() == ARM::GPRRegBankID ||
129 RegBank->getID() == ARM::FPRRegBankID) &&
132 if (RegBank->getID() == ARM::FPRRegBankID) {
250 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
254 if (RegBank == ARM::GPRRegBankID) {
268 if (RegBank == ARM::FPRRegBankID) {
896 unsigned RegBank = RBI.getRegBank(Reg, MRI, TRI)->getID();
904 const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize)
[all...] |
| ARMRegisterBankInfo.cpp | 53 PM.RegBank->getID() == RegBankID;
434 (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
|
| /external/llvm/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 45 const RegisterBank &RegBank) {
46 VRegInfo[Reg].first = &RegBank;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| X86InstructionSelector.cpp | 193 llvm_unreachable("Unknown RegBank!");
199 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI);
200 return getRegClass(Ty, RegBank);
[all...] |
