| /external/u-boot/board/freescale/corenet_ds/ |
| p4080ds_ddr.c | 72 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031
92 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
124 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
156 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
188 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
220 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
252 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
284 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
316 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2,
|
| /external/u-boot/include/configs/km/ |
| km8321-common.h | 76 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
| km8309-common.h | 111 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
| /external/u-boot/board/freescale/mpc8308rdb/ |
| sdram.c | 53 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
|
| /external/u-boot/board/freescale/mpc8315erdb/ |
| sdram.c | 74 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
|
| /external/u-boot/board/gdsys/mpc8308/ |
| sdram.c | 54 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
|
| /external/u-boot/board/mpc8308_p1m/ |
| sdram.c | 49 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
|
| /external/u-boot/board/freescale/mpc832xemds/ |
| mpc832xemds.c | 141 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
|
| /external/u-boot/include/configs/ |
| km8360.h | 76 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
| MPC8308RDB.h | 176 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
|
| MPC8323ERDB.h | 131 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
| MPC832XEMDS.h | 141 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
| mpc8308_p1m.h | 178 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
|
| MPC8315ERDB.h | 148 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
|
| MPC8349EMDS.h | 115 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
| MPC837XEMDS.h | 170 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
|
| MPC837XERDB.h | 196 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
|
| hrcon.h | 165 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
|
| strider.h | 165 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
|
| /external/u-boot/board/freescale/mpc8323erdb/ |
| mpc8323erdb.c | 119 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
|
| /external/u-boot/board/freescale/mpc837xerdb/ |
| mpc837xerdb.c | 116 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
|
| /external/u-boot/board/freescale/mpc8349emds/ |
| mpc8349emds.c | 108 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
|
| /external/u-boot/board/freescale/mpc837xemds/ |
| mpc837xemds.c | 276 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
|
| /external/u-boot/board/keymile/km83xx/ |
| km83xx.c | 304 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
|
