1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2006 Freescale Semiconductor, Inc. 4 * Dave Liu <daveliu (at) freescale.com> 5 * 6 * Copyright (C) 2007 Logic Product Development, Inc. 7 * Peter Barada <peterb (at) logicpd.com> 8 * 9 * Copyright (C) 2007 MontaVista Software, Inc. 10 * Anton Vorontsov <avorontsov (at) ru.mvista.com> 11 * 12 * (C) Copyright 2008 - 2010 13 * Heiko Schocher, DENX Software Engineering, hs (at) denx.de. 14 */ 15 16 #include <common.h> 17 #include <ioports.h> 18 #include <mpc83xx.h> 19 #include <i2c.h> 20 #include <miiphy.h> 21 #include <asm/io.h> 22 #include <asm/mmu.h> 23 #include <asm/processor.h> 24 #include <pci.h> 25 #include <linux/libfdt.h> 26 #include <post.h> 27 28 #include "../common/common.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; 33 34 const qe_iop_conf_t qe_iop_conf_tab[] = { 35 /* port pin dir open_drain assign */ 36 #if defined(CONFIG_MPC8360) 37 /* MDIO */ 38 {0, 1, 3, 0, 2}, /* MDIO */ 39 {0, 2, 1, 0, 1}, /* MDC */ 40 41 /* UCC4 - UEC */ 42 {1, 14, 1, 0, 1}, /* TxD0 */ 43 {1, 15, 1, 0, 1}, /* TxD1 */ 44 {1, 20, 2, 0, 1}, /* RxD0 */ 45 {1, 21, 2, 0, 1}, /* RxD1 */ 46 {1, 18, 1, 0, 1}, /* TX_EN */ 47 {1, 26, 2, 0, 1}, /* RX_DV */ 48 {1, 27, 2, 0, 1}, /* RX_ER */ 49 {1, 24, 2, 0, 1}, /* COL */ 50 {1, 25, 2, 0, 1}, /* CRS */ 51 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ 52 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ 53 54 /* DUART - UART2 */ 55 {5, 0, 1, 0, 2}, /* UART2_SOUT */ 56 {5, 2, 1, 0, 1}, /* UART2_RTS */ 57 {5, 3, 2, 0, 2}, /* UART2_SIN */ 58 {5, 1, 2, 0, 3}, /* UART2_CTS */ 59 #elif !defined(CONFIG_MPC8309) 60 /* Local Bus */ 61 {0, 16, 1, 0, 3}, /* LA00 */ 62 {0, 17, 1, 0, 3}, /* LA01 */ 63 {0, 18, 1, 0, 3}, /* LA02 */ 64 {0, 19, 1, 0, 3}, /* LA03 */ 65 {0, 20, 1, 0, 3}, /* LA04 */ 66 {0, 21, 1, 0, 3}, /* LA05 */ 67 {0, 22, 1, 0, 3}, /* LA06 */ 68 {0, 23, 1, 0, 3}, /* LA07 */ 69 {0, 24, 1, 0, 3}, /* LA08 */ 70 {0, 25, 1, 0, 3}, /* LA09 */ 71 {0, 26, 1, 0, 3}, /* LA10 */ 72 {0, 27, 1, 0, 3}, /* LA11 */ 73 {0, 28, 1, 0, 3}, /* LA12 */ 74 {0, 29, 1, 0, 3}, /* LA13 */ 75 {0, 30, 1, 0, 3}, /* LA14 */ 76 {0, 31, 1, 0, 3}, /* LA15 */ 77 78 /* MDIO */ 79 {3, 4, 3, 0, 2}, /* MDIO */ 80 {3, 5, 1, 0, 2}, /* MDC */ 81 82 /* UCC4 - UEC */ 83 {1, 18, 1, 0, 1}, /* TxD0 */ 84 {1, 19, 1, 0, 1}, /* TxD1 */ 85 {1, 22, 2, 0, 1}, /* RxD0 */ 86 {1, 23, 2, 0, 1}, /* RxD1 */ 87 {1, 26, 2, 0, 1}, /* RxER */ 88 {1, 28, 2, 0, 1}, /* Rx_DV */ 89 {1, 30, 1, 0, 1}, /* TxEN */ 90 {1, 31, 2, 0, 1}, /* CRS */ 91 {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */ 92 #endif 93 94 /* END of table */ 95 {0, 0, 0, 0, QE_IOP_TAB_END}, 96 }; 97 98 #if defined(CONFIG_SUVD3) 99 const uint upma_table[] = { 100 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */ 101 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */ 102 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */ 103 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */ 104 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */ 105 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */ 106 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */ 107 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ 108 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */ 109 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */ 110 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */ 111 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */ 112 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */ 113 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */ 114 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */ 115 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */ 116 }; 117 #endif 118 119 static int piggy_present(void) 120 { 121 struct km_bec_fpga __iomem *base = 122 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; 123 124 return in_8(&base->bprth) & PIGGY_PRESENT; 125 } 126 127 #if defined(CONFIG_KMVECT1) 128 int ethernet_present(void) 129 { 130 /* ethernet port connected to simple switch without piggy */ 131 return 1; 132 } 133 #else 134 int ethernet_present(void) 135 { 136 return piggy_present(); 137 } 138 #endif 139 140 141 int board_early_init_r(void) 142 { 143 struct km_bec_fpga *base = 144 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; 145 #if defined(CONFIG_SUVD3) 146 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 147 fsl_lbc_t *lbc = &immap->im_lbc; 148 u32 *mxmr = &lbc->mamr; 149 #endif 150 151 #if defined(CONFIG_MPC8360) 152 unsigned short svid; 153 /* 154 * Because of errata in the UCCs, we have to write to the reserved 155 * registers to slow the clocks down. 156 */ 157 svid = SVR_REV(mfspr(SVR)); 158 switch (svid) { 159 case 0x0020: 160 /* 161 * MPC8360ECE.pdf QE_ENET10 table 4: 162 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) 163 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) 164 */ 165 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000); 166 break; 167 case 0x0021: 168 /* 169 * MPC8360ECE.pdf QE_ENET10 table 4: 170 * IMMR + 0x14AC[24:27] = 1010 171 */ 172 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac), 173 0x00000050, 0x000000a0); 174 break; 175 } 176 #endif 177 178 /* enable the PHY on the PIGGY */ 179 setbits_8(&base->pgy_eth, 0x01); 180 /* enable the Unit LED (green) */ 181 setbits_8(&base->oprth, WRL_BOOT); 182 /* enable Application Buffer */ 183 setbits_8(&base->oprtl, OPRTL_XBUFENA); 184 185 #if defined(CONFIG_SUVD3) 186 /* configure UPMA for APP1 */ 187 upmconfig(UPMA, (uint *) upma_table, 188 sizeof(upma_table) / sizeof(uint)); 189 out_be32(mxmr, CONFIG_SYS_MAMR); 190 #endif 191 return 0; 192 } 193 194 int misc_init_r(void) 195 { 196 ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 197 return 0; 198 } 199 200 #if defined(CONFIG_KMVECT1) 201 #include <mv88e6352.h> 202 /* Marvell MV88E6122 switch configuration */ 203 static struct mv88e_sw_reg extsw_conf[] = { 204 /* port 1, FRONT_MDI, autoneg */ 205 { PORT(1), PORT_PHY, NO_SPEED_FOR }, 206 { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 207 { PHY(1), PHY_1000_CTRL, NO_ADV }, 208 { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 209 { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 210 FULL_DUPLEX }, 211 /* port 2, unused */ 212 { PORT(2), PORT_CTRL, PORT_DIS }, 213 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 214 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 215 /* port 3, BP_MII (CPU), PHY mode, 100BASE */ 216 { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 217 /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */ 218 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 219 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 220 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 221 /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */ 222 { PORT(5), PORT_STATUS, NO_PHY_DETECT }, 223 { PORT(5), PORT_PHY, SPEED_1000_FOR }, 224 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 225 /* 226 * Errata Fix: 1.9V Output from Internal 1.8V Regulator, 227 * acc . MV-S300889-00D.pdf , clause 4.5 228 */ 229 { PORT(5), 0x1A, 0xADB1 }, 230 /* port 6, unused, this port has no phy */ 231 { PORT(6), PORT_CTRL, PORT_DIS }, 232 /* 233 * Errata Fix: 1.9V Output from Internal 1.8V Regulator, 234 * acc . MV-S300889-00D.pdf , clause 4.5 235 */ 236 { PORT(5), 0x1A, 0xADB1 }, 237 }; 238 #endif 239 240 int last_stage_init(void) 241 { 242 #if defined(CONFIG_KMVECT1) 243 struct km_bec_fpga __iomem *base = 244 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; 245 u8 tmp_reg; 246 247 /* Release mv88e6122 from reset */ 248 tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */ 249 out_8(&base->res1[0], tmp_reg); /* GP28 as output */ 250 tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */ 251 out_8(&base->gprt3, tmp_reg); 252 253 /* configure MV88E6122 switch */ 254 char *name = "UEC2"; 255 256 if (miiphy_set_current_dev(name)) 257 return 0; 258 259 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 260 ARRAY_SIZE(extsw_conf)); 261 262 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 263 264 if (piggy_present()) { 265 env_set("ethact", "UEC2"); 266 env_set("netdev", "eth1"); 267 puts("using PIGGY for network boot\n"); 268 } else { 269 env_set("netdev", "eth0"); 270 puts("using frontport for network boot\n"); 271 } 272 #endif 273 274 #if defined(CONFIG_KMCOGE5NE) 275 struct bfticu_iomap *base = 276 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; 277 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; 278 279 if (dip_switch != 0) { 280 /* start bootloader */ 281 puts("DIP: Enabled\n"); 282 env_set("actual_bank", "0"); 283 } 284 #endif 285 set_km_env(); 286 return 0; 287 } 288 289 static int fixed_sdram(void) 290 { 291 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 292 u32 msize = 0; 293 u32 ddr_size; 294 u32 ddr_size_log2; 295 296 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); 297 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); 298 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 299 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 300 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 301 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 302 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 303 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 304 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 305 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 306 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 307 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 308 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); 309 udelay(200); 310 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 311 312 msize = CONFIG_SYS_DDR_SIZE << 20; 313 disable_addr_trans(); 314 msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); 315 enable_addr_trans(); 316 msize /= (1024 * 1024); 317 if (CONFIG_SYS_DDR_SIZE != msize) { 318 for (ddr_size = msize << 20, ddr_size_log2 = 0; 319 (ddr_size > 1); 320 ddr_size = ddr_size >> 1, ddr_size_log2++) 321 if (ddr_size & 1) 322 return -1; 323 out_be32(&im->sysconf.ddrlaw[0].ar, 324 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE))); 325 out_be32(&im->ddr.csbnds[0].csbnds, 326 (((msize / 16) - 1) & 0xff)); 327 } 328 329 return msize; 330 } 331 332 int dram_init(void) 333 { 334 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 335 u32 msize = 0; 336 337 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 338 return -ENXIO; 339 340 out_be32(&im->sysconf.ddrlaw[0].bar, 341 CONFIG_SYS_DDR_BASE & LAWBAR_BAR); 342 msize = fixed_sdram(); 343 344 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 345 /* 346 * Initialize DDR ECC byte 347 */ 348 ddr_enable_ecc(msize * 1024 * 1024); 349 #endif 350 351 /* return total bus SDRAM size(bytes) -- DDR */ 352 gd->ram_size = msize * 1024 * 1024; 353 354 return 0; 355 } 356 357 int checkboard(void) 358 { 359 puts("Board: Keymile " CONFIG_KM_BOARD_NAME); 360 361 if (piggy_present()) 362 puts(" with PIGGY."); 363 puts("\n"); 364 return 0; 365 } 366 367 int ft_board_setup(void *blob, bd_t *bd) 368 { 369 ft_cpu_setup(blob, bd); 370 371 return 0; 372 } 373 374 #if defined(CONFIG_HUSH_INIT_VAR) 375 int hush_init_var(void) 376 { 377 ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); 378 return 0; 379 } 380 #endif 381 382 #if defined(CONFIG_POST) 383 int post_hotkeys_pressed(void) 384 { 385 int testpin = 0; 386 struct km_bec_fpga *base = 387 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; 388 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); 389 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; 390 debug("post_hotkeys_pressed: %d\n", !testpin); 391 return testpin; 392 } 393 394 ulong post_word_load(void) 395 { 396 void* addr = (ulong *) (CPM_POST_WORD_ADDR); 397 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr)); 398 return in_le32(addr); 399 400 } 401 void post_word_store(ulong value) 402 { 403 void* addr = (ulong *) (CPM_POST_WORD_ADDR); 404 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value); 405 out_le32(addr, value); 406 } 407 408 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 409 { 410 *vstart = CONFIG_SYS_MEMTEST_START; 411 *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START; 412 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size); 413 414 return 0; 415 } 416 #endif 417
