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      1 /*
      2  * (C) Copyright 2013
      3  * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach (at) gdsys.cc
      4  *
      5  * based on P1022DS.h
      6  *
      7  * See file CREDITS for list of people who contributed to this
      8  * project.
      9  *
     10  * This program is free software; you can redistribute it and/or
     11  * modify it under the terms of the GNU General Public License as
     12  * published by the Free Software Foundation; either version 2 of
     13  * the License, or (at your option) any later version.
     14  *
     15  * This program is distributed in the hope that it will be useful,
     16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
     18  * GNU General Public License for more details.
     19  *
     20  * You should have received a copy of the GNU General Public License
     21  * along with this program; if not, write to the Free Software
     22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     23  * MA 02111-1307 USA
     24  */
     25 
     26 #ifndef __CONFIG_H
     27 #define __CONFIG_H
     28 
     29 #ifdef CONFIG_SDCARD
     30 #define CONFIG_RAMBOOT_SDCARD
     31 #endif
     32 
     33 #ifdef CONFIG_SPIFLASH
     34 #define CONFIG_RAMBOOT_SPIFLASH
     35 #endif
     36 
     37 /* High Level Configuration Options */
     38 #define CONFIG_CONTROLCENTERD
     39 #define CONFIG_MP			/* support multiple processors */
     40 
     41 #define CONFIG_ENABLE_36BIT_PHYS
     42 
     43 #ifdef CONFIG_PHYS_64BIT
     44 #define CONFIG_ADDR_MAP
     45 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
     46 #endif
     47 
     48 #define CONFIG_L2_CACHE
     49 #define CONFIG_BTB
     50 
     51 #define CONFIG_SYS_CLK_FREQ	66666600
     52 #define CONFIG_DDR_CLK_FREQ	66666600
     53 
     54 #define CONFIG_SYS_RAMBOOT
     55 
     56 #ifdef CONFIG_TRAILBLAZER
     57 
     58 #define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
     59 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
     60 
     61 /*
     62  * Config the L2 Cache
     63  */
     64 #define CONFIG_SYS_INIT_L2_ADDR		0xf8fc0000
     65 #ifdef CONFIG_PHYS_64BIT
     66 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8fc0000ull
     67 #else
     68 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
     69 #endif
     70 #define CONFIG_SYS_L2_SIZE		(256 << 10)
     71 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
     72 
     73 #else /* CONFIG_TRAILBLAZER */
     74 
     75 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
     76 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
     77 
     78 #endif /* CONFIG_TRAILBLAZER */
     79 
     80 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
     81 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
     82 
     83 /*
     84  * Memory map
     85  *
     86  * 0x0000_0000	0x3fff_ffff	DDR			1G Cacheable
     87  * 0xc000_0000	0xdfff_ffff	PCI Express Mem		512M non-cacheable
     88  * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
     89  *
     90  * Localbus non-cacheable
     91  * 0xe000_0000	0xe00f_ffff	eLBC			1M non-cacheable
     92  * 0xf8fc0000	0xf8ff_ffff	L2 SRAM			256k Cacheable
     93  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
     94  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
     95  */
     96 
     97 #define CONFIG_SYS_INIT_RAM_LOCK
     98 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
     99 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* used area in RAM */
    100 #define CONFIG_SYS_GBL_DATA_OFFSET	\
    101 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
    102 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
    103 
    104 #ifdef CONFIG_TRAILBLAZER
    105 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */
    106 #define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
    107 #else
    108 #define CONFIG_SYS_CCSRBAR		0xffe00000
    109 #endif
    110 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
    111 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR	(CONFIG_SYS_CCSRBAR+0xf200)
    112 
    113 /*
    114  * DDR Setup
    115  */
    116 
    117 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
    118 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
    119 #define CONFIG_SYS_SDRAM_SIZE 1024
    120 #define CONFIG_VERY_BIG_RAM
    121 
    122 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
    123 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
    124 
    125 #define CONFIG_SYS_MEMTEST_START	0x00000000
    126 #define CONFIG_SYS_MEMTEST_END		0x3fffffff
    127 
    128 #ifdef CONFIG_TRAILBLAZER
    129 #define CONFIG_SPD_EEPROM
    130 #define SPD_EEPROM_ADDRESS 0x52
    131 /*#define CONFIG_FSL_DDR_INTERACTIVE*/
    132 #endif
    133 
    134 /*
    135  * Local Bus Definitions
    136  */
    137 
    138 #define CONFIG_SYS_ELBC_BASE		0xe0000000
    139 #ifdef CONFIG_PHYS_64BIT
    140 #define CONFIG_SYS_ELBC_BASE_PHYS	0xfe0000000ull
    141 #else
    142 #define CONFIG_SYS_ELBC_BASE_PHYS	CONFIG_SYS_ELBC_BASE
    143 #endif
    144 
    145 #define CONFIG_UART_BR_PRELIM  \
    146 	(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
    147 #define CONFIG_UART_OR_PRELIM	(OR_AM_32KB | 0xff7)
    148 
    149 #define CONFIG_SYS_BR0_PRELIM	0 /* CS0 was originally intended for FPGA */
    150 #define CONFIG_SYS_OR0_PRELIM	0 /* debugging, was never used */
    151 
    152 #define CONFIG_SYS_BR1_PRELIM	CONFIG_UART_BR_PRELIM
    153 #define CONFIG_SYS_OR1_PRELIM	CONFIG_UART_OR_PRELIM
    154 
    155 /*
    156  * Serial Port
    157  */
    158 #define CONFIG_SYS_NS16550_SERIAL
    159 #define CONFIG_SYS_NS16550_REG_SIZE	1
    160 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
    161 
    162 #define CONFIG_SYS_BAUDRATE_TABLE	\
    163 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
    164 
    165 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
    166 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
    167 
    168 /*
    169  * I2C
    170  */
    171 #define CONFIG_SYS_I2C
    172 #define CONFIG_SYS_I2C_FSL
    173 #define CONFIG_SYS_FSL_I2C_SPEED	400000
    174 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
    175 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
    176 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
    177 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
    178 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
    179 
    180 #ifndef CONFIG_TRAILBLAZER
    181 #endif
    182 
    183 #define CONFIG_PCA9698			/* NXP PCA9698 */
    184 
    185 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
    186 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
    187 
    188 #ifndef CONFIG_TRAILBLAZER
    189 /*
    190  * eSPI - Enhanced SPI
    191  */
    192 #define CONFIG_HARD_SPI
    193 
    194 #define CONFIG_SF_DEFAULT_SPEED		10000000
    195 #define CONFIG_SF_DEFAULT_MODE		0
    196 #endif
    197 
    198 /*
    199  * MMC
    200  */
    201 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
    202 
    203 #ifndef CONFIG_TRAILBLAZER
    204 
    205 /*
    206  * Video
    207  */
    208 #define CONFIG_FSL_DIU_FB
    209 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
    210 
    211 /*
    212  * General PCI
    213  * Memory space is mapped 1-1, but I/O space must start from 0.
    214  */
    215 #define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
    216 #define CONFIG_PCI_INDIRECT_BRIDGE
    217 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
    218 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
    219 
    220 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
    221 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
    222 
    223 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
    224 #ifdef CONFIG_PHYS_64BIT
    225 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
    226 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
    227 #else
    228 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
    229 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
    230 #endif
    231 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
    232 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
    233 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
    234 #ifdef CONFIG_PHYS_64BIT
    235 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
    236 #else
    237 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
    238 #endif
    239 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
    240 
    241 /*
    242  * SATA
    243  */
    244 #define CONFIG_LBA48
    245 
    246 #define CONFIG_SYS_SATA_MAX_DEVICE	2
    247 #define CONFIG_SATA1
    248 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
    249 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
    250 #define CONFIG_SATA2
    251 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
    252 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
    253 
    254 /*
    255  * Ethernet
    256  */
    257 
    258 #define CONFIG_TSECV2
    259 
    260 #define CONFIG_MII			/* MII PHY management */
    261 #define CONFIG_TSEC1		1
    262 #define CONFIG_TSEC1_NAME	"eTSEC1"
    263 #define CONFIG_TSEC2		1
    264 #define CONFIG_TSEC2_NAME	"eTSEC2"
    265 
    266 #define TSEC1_PHY_ADDR		0
    267 #define TSEC2_PHY_ADDR		1
    268 
    269 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
    270 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
    271 
    272 #define TSEC1_PHYIDX		0
    273 #define TSEC2_PHYIDX		0
    274 
    275 #define CONFIG_ETHPRIME		"eTSEC1"
    276 
    277 /*
    278  * USB
    279  */
    280 
    281 #define CONFIG_HAS_FSL_DR_USB
    282 #define CONFIG_USB_EHCI_FSL
    283 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
    284 
    285 #endif /* CONFIG_TRAILBLAZER */
    286 
    287 /*
    288  * Environment
    289  */
    290 #if defined(CONFIG_TRAILBLAZER)
    291 #define CONFIG_ENV_SIZE		0x2000		/* 8KB */
    292 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
    293 #define CONFIG_ENV_SPI_BUS	0
    294 #define CONFIG_ENV_SPI_CS	0
    295 #define CONFIG_ENV_SPI_MAX_HZ	10000000
    296 #define CONFIG_ENV_SPI_MODE	0
    297 #define CONFIG_ENV_SIZE		0x2000		/* 8KB */
    298 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
    299 #define CONFIG_ENV_SECT_SIZE	0x10000
    300 #elif defined(CONFIG_RAMBOOT_SDCARD)
    301 #define CONFIG_FSL_FIXED_MMC_LOCATION
    302 #define CONFIG_ENV_SIZE		0x2000
    303 #define CONFIG_SYS_MMC_ENV_DEV	0
    304 #endif
    305 
    306 #define CONFIG_SYS_EXTRA_ENV_RELOC
    307 
    308 /*
    309  * Command line configuration.
    310  */
    311 
    312 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
    313 
    314 #ifndef CONFIG_TRAILBLAZER
    315 /*
    316  * Board initialisation callbacks
    317  */
    318 #define CONFIG_MISC_INIT_R
    319 #endif /* CONFIG_TRAILBLAZER */
    320 
    321 /*
    322  * Miscellaneous configurable options
    323  */
    324 #define CONFIG_HW_WATCHDOG
    325 #define CONFIG_LOADS_ECHO
    326 #define CONFIG_SYS_LOADS_BAUD_CHANGE
    327 
    328 /*
    329  * For booting Linux, the board info and command line data
    330  * have to be in the first 64 MB of memory, since this is
    331  * the maximum mapped by the Linux kernel during initialization.
    332  */
    333 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Linux Memory map */
    334 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
    335 
    336 /*
    337  * Environment Configuration
    338  */
    339 
    340 #ifdef CONFIG_TRAILBLAZER
    341 #define	CONFIG_EXTRA_ENV_SETTINGS				\
    342 	"mp_holdoff=1\0"
    343 
    344 #else
    345 
    346 #define CONFIG_HOSTNAME		"controlcenterd"
    347 #define CONFIG_ROOTPATH		"/opt/nfsroot"
    348 #define CONFIG_BOOTFILE		"uImage"
    349 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP */
    350 
    351 #define CONFIG_LOADADDR		1000000
    352 
    353 #define	CONFIG_EXTRA_ENV_SETTINGS				\
    354 	"netdev=eth0\0"						\
    355 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
    356 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
    357 	"tftpflash=tftpboot $loadaddr $uboot && "		\
    358 		"protect off $ubootaddr +$filesize && "		\
    359 		"erase $ubootaddr +$filesize && "		\
    360 		"cp.b $loadaddr $ubootaddr $filesize && "	\
    361 		"protect on $ubootaddr +$filesize && "		\
    362 		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
    363 	"consoledev=ttyS1\0"					\
    364 	"ramdiskaddr=2000000\0"					\
    365 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
    366 	"fdtaddr=1e00000\0"					\
    367 	"fdtfile=controlcenterd.dtb\0"				\
    368 	"bdev=sda3\0"
    369 
    370 /* these are used and NUL-terminated in env_default.h */
    371 #define CONFIG_NFSBOOTCOMMAND						\
    372 	"setenv bootargs root=/dev/nfs rw "				\
    373 	"nfsroot=$serverip:$rootpath "					\
    374 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
    375 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
    376 	"tftp $loadaddr $bootfile;"					\
    377 	"tftp $fdtaddr $fdtfile;"					\
    378 	"bootm $loadaddr - $fdtaddr"
    379 
    380 #define CONFIG_RAMBOOTCOMMAND						\
    381 	"setenv bootargs root=/dev/ram rw "				\
    382 	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
    383 	"tftp $ramdiskaddr $ramdiskfile;"				\
    384 	"tftp $loadaddr $bootfile;"					\
    385 	"tftp $fdtaddr $fdtfile;"					\
    386 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
    387 
    388 #define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
    389 
    390 #endif /* CONFIG_TRAILBLAZER */
    391 
    392 #endif
    393