| /external/capstone/suite/MC/Mips/ |
| micromips-loadstore-unaligned-EB.s.cs | 1 # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
|
| micromips-movcond-instructions-EB.s.cs | 1 # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
|
| micromips-multiply-instructions-EB.s.cs | 1 # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
|
| test_elm_insert.s.cs | 1 # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
|
| test_elm_insve.s.cs | 1 # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
|
| micromips-loadstore-instructions-EB.s.cs | 1 # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
|
| micromips-shift-instructions-EB.s.cs | 1 # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
|
| mips_directives.s.cs | 1 # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
|
| nabi-regs.s.cs | 1 # CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
|
| test_vec.s.cs | 1 # CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
|
| /external/capstone/bindings/python/ |
| test_basic.py | 45 (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
47 (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", 0),
48 (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", 0),
50 (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0),
51 (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
52 (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", 0),
53 (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", 0),
|
| test_detail.py | 40 (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
42 (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", 0),
43 (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", 0),
44 (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0),
45 (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", 0),
46 (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", 0),
|
| test_lite.py | 31 (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", 0),
34 (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", 0),
35 (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
|
| test_mips.py | 16 (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
18 (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)"),
19 (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)"),
|
| /external/capstone/arch/AArch64/ |
| AArch64Module.c | 17 if (ud->mode & ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_ARM | CS_MODE_BIG_ENDIAN))
39 handle->big_endian = (((cs_mode)value & CS_MODE_BIG_ENDIAN) != 0);
|
| /external/capstone/arch/Sparc/ |
| SparcModule.c | 17 if (ud->mode & ~(CS_MODE_BIG_ENDIAN | CS_MODE_V9))
43 handle->big_endian = (((cs_mode)value & CS_MODE_BIG_ENDIAN) != 0);
|
| /external/capstone/suite/fuzz/ |
| fuzz_harness.c | 62 (cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
72 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
77 (cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
87 CS_MODE_BIG_ENDIAN,
92 CS_MODE_BIG_ENDIAN,
97 (cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
|
| /external/capstone/suite/ |
| benchmark.py | 31 (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0),
34 (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0),
35 (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
36 (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", 0),
|
| fuzz.py | 37 (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0),
40 (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0),
41 (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
42 (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", 0),
|
| test_group_name.py | 216 GroupTest('mips', CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN, mips_dict),
217 GroupTest('ppc', CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, ppc_dict),
218 GroupTest('sparc', CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, sparc_dict),
219 GroupTest('sysz', CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN, sysz_dict),
221 GroupTest('xcore', CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN, xcore_dict),
|
| /external/capstone/arch/ARM/ |
| ARMModule.c | 18 CS_MODE_MCLASS | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN))
52 handle->big_endian = ((handle->mode & CS_MODE_BIG_ENDIAN) != 0);
|
| /external/capstone/arch/Mips/ |
| MipsModule.c | 19 CS_MODE_MIPSGP64 | CS_MODE_BIG_ENDIAN))
50 handle->big_endian = ((handle->mode & CS_MODE_BIG_ENDIAN) != 0);
|
| /external/capstone/arch/PowerPC/ |
| PPCModule.c | 18 CS_MODE_BIG_ENDIAN))
44 handle->big_endian = (((cs_mode)value & CS_MODE_BIG_ENDIAN) != 0);
|
| /external/capstone/suite/MC/Sparc/ |
| sparc-atomic-instructions.s.cs | 1 # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
|
| sparcv8-instructions.s.cs | 1 # CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
|
