| /external/u-boot/board/freescale/t1040qds/ |
| ddr.h | 44 #error DDR type not defined
|
| /external/u-boot/board/freescale/t104xrdb/ |
| ddr.h | 46 #error DDR type not defined
|
| /external/libavc/encoder/ |
| ih264e_rc_mem_interface.h | 82 DDR = 3
|
| irc_mem_req_and_acq.h | 82 DDR = 3
|
| ih264e_modify_frm_rate.c | 120 ALIGN_128_BYTE, PERSISTENT, DDR);
|
| irc_mb_model_based.c | 65 ALIGN_128_BYTE, PERSISTENT, DDR);
|
| irc_fixed_point_error_bits.c | 78 ALIGN_128_BYTE, PERSISTENT, DDR);
|
| irc_est_sad.c | 73 ALIGN_128_BYTE, PERSISTENT, DDR);
|
| ih264e_time_stamp.c | 239 ALIGN_128_BYTE, PERSISTENT, DDR);
429 ALIGN_128_BYTE, PERSISTENT, DDR);
|
| ih264e_rc_mem_interface.c | 299 /* only DDR memory is available */
300 rc_memtab->e_mem_region = DDR;
|
| /external/libhevc/encoder/ |
| mem_req_and_acq.h | 50 DDR = 3
|
| mb_model_based.c | 73 DDR);
|
| rc_sad_acc.c | 74 &ps_memtab[i4_mem_tab_idx], sizeof(sad_acc_t), MEM_TAB_ALIGNMENT, PERSISTENT, DDR);
|
| fixed_point_error_bits.c | 78 &ps_memtab[i4_mem_tab_idx], sizeof(error_bits_t), MEM_TAB_ALIGNMENT, PERSISTENT, DDR);
|
| init_qp.c | 72 &ps_memtab[i4_mem_tab_idx], sizeof(init_qp_t), MEM_TAB_ALIGNMENT, PERSISTENT, DDR);
|
| est_sad.c | 72 &ps_memtab[i4_mem_tab_idx], sizeof(est_sad_t), MEM_TAB_ALIGNMENT, PERSISTENT, DDR);
|
| /external/u-boot/board/freescale/ls1021aqds/ |
| ddr.h | 49 #error DDR type not defined
|
| /external/u-boot/board/freescale/ls1043aqds/ |
| ddr.h | 52 #error DDR type not defined
|
| /external/u-boot/board/imgtec/xilfpga/ |
| README | 20 - 128Mbyte DDR RAM at 0x0000_0000
37 DDR initialization is already handled by a HW IP block.
|
| /external/u-boot/drivers/video/ |
| bus_vcxk.c | 23 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
26 writel(PIN, &pio->PORT.DDR); \
44 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
45 if (I0O1) DDR |= PIN; else DDR &= ~PIN;
|
| /external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| README.lsch3 | 12 DDR Layout
14 Entire DDR region splits into two regions.
19 All DDR memory is marked as cache-enabled.
22 end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
145 Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where
149 can be replaced with the addresses of DDR to
|
| /external/u-boot/arch/arm/mach-tegra/tegra30/ |
| pinmux.c | 98 PIN(VI_D0_PT4, DDR, RSVD2, VI, RSVD4),
99 PIN(VI_D1_PD5, DDR, SDMMC2, VI, RSVD4),
100 PIN(VI_D2_PL0, DDR, SDMMC2, VI, RSVD4),
101 PIN(VI_D3_PL1, DDR, SDMMC2, VI, RSVD4),
102 PIN(VI_D4_PL2, DDR, SDMMC2, VI, RSVD4),
103 PIN(VI_D5_PL3, DDR, SDMMC2, VI, RSVD4),
104 PIN(VI_D6_PL4, DDR, SDMMC2, VI, RSVD4),
105 PIN(VI_D7_PL5, DDR, SDMMC2, VI, RSVD4),
106 PIN(VI_D8_PL6, DDR, SDMMC2, VI, RSVD4),
107 PIN(VI_D9_PL7, DDR, SDMMC2, VI, RSVD4)
[all...] |
| /external/u-boot/arch/arm/cpu/arm926ejs/spear/ |
| spr_misc.c | 19 #define DDR 1
209 sram_setfreq(DDR, frequency);
210 printf("DDR frequency changed to %u\n", frequency);
|
| /external/u-boot/include/net/pfe_eth/ |
| pfe_eth.h | 56 #error DDR mapping above 12MiB
|
| /external/u-boot/board/freescale/t102xqds/ |
| ddr.c | 50 #error DDR type not defined
76 /* Get clk_adjust according to the board ddr freqency and n_banks
146 /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
147 * set DDR bus width to 32bit for T1023
153 /* for DDR bus 32bit test on T1024 */
179 /* DDR has been initialised by first stage boot loader */
|
