1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __DDR_H__ 7 #define __DDR_H__ 8 struct board_specific_parameters { 9 u32 n_ranks; 10 u32 datarate_mhz_high; 11 u32 rank_gb; 12 u32 clk_adjust; 13 u32 wrlvl_start; 14 u32 wrlvl_ctl_2; 15 u32 wrlvl_ctl_3; 16 }; 17 18 /* 19 * These tables contain all valid speeds we want to override with board 20 * specific parameters. datarate_mhz_high values need to be in ascending order 21 * for each n_ranks group. 22 */ 23 24 static const struct board_specific_parameters udimm0[] = { 25 /* 26 * memory controller 0 27 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 29 */ 30 #ifdef CONFIG_SYS_FSL_DDR4 31 {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 32 {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, 33 {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, 34 {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, 35 {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,}, 36 #elif defined(CONFIG_SYS_FSL_DDR3) 37 {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, 38 {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, 39 {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 40 {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, 41 {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, 42 {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 43 #else 44 #error DDR type not defined 45 #endif 46 {} 47 }; 48 49 static const struct board_specific_parameters *udimms[] = { 50 udimm0, 51 }; 52 #endif 53
