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    Searched refs:DDRIOCCC_CH_OFFSET (Results 1 - 6 of 6) sorted by null

  /external/u-boot/arch/x86/cpu/quark/
mrc_util.c 589 reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET;
609 reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET;
615 reg = CMDDLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; /* PO */
623 reg = CMDCFGREG0 + channel * DDRIOCCC_CH_OFFSET;
662 reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET;
681 reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET;
711 reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET;
725 reg += (channel * DDRIOCCC_CH_OFFSET);
731 reg += (channel * DDRIOCCC_CH_OFFSET);
735 reg += (channel * DDRIOCCC_CH_OFFSET);
    [all...]
smc.c 283 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET,
287 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET,
291 CMDPTRREG + ch * DDRIOCCC_CH_OFFSET,
493 CMDOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET,
498 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET,
503 CMDRCOMPODT + ch * DDRIOCCC_CH_OFFSET,
510 CMDPMDLYREG4 + ch * DDRIOCCC_CH_OFFSET,
518 CMDPMDLYREG3 + ch * DDRIOCCC_CH_OFFSET,
522 CMDPMDLYREG2 + ch * DDRIOCCC_CH_OFFSET,
526 CMDPMDLYREG1 + ch * DDRIOCCC_CH_OFFSET,
    [all...]
smc.h 162 #define DDRIOCCC_CH_OFFSET 0x0800
  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
meminit_utils.c 452 reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET);
470 reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
478 reg = CMDDLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); // PO
484 reg = CMDCFGREG0 + (channel * DDRIOCCC_CH_OFFSET);
524 reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET);
541 reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
569 reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
581 reg += (channel * DDRIOCCC_CH_OFFSET);
586 reg += (channel * DDRIOCCC_CH_OFFSET);
589 reg += (channel * DDRIOCCC_CH_OFFSET);
    [all...]
meminit.c 519 isbM32m(DDRPHY, (CMDPMCONFIG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT20, BIT20); // SPID_INIT_COMPLETE=0
521 isbM32m(DDRPHY, (CMDCFGREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT2, BIT2); // IOBUFACTRST_N=0
523 isbM32m(DDRPHY, (CMDPTRREG + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT0, BIT0); // WRPTRENABLE=0
593 isbM32m(DDRPHY, (CMDOBSCKEBBCTL + (channel_i * DDRIOCCC_CH_OFFSET)), 0, (BIT23));
596 isbM32m(DDRPHY, (CMDCFGREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), 0, (BIT1|BIT0));
599 isbM32m(DDRPHY, (CMDRCOMPODT + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x03<<5)|(0x03<<0)), ((BIT9|BIT8|BIT7|BIT6|BIT5)|(BIT4|BIT3|BIT2|BIT1|BIT0)));
602 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
603 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
604 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
605 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24 (…)
    [all...]
gen5_iosf_sb_definitions.h 470 #define DDRIOCCC_CH_OFFSET 0x0800

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