1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2012-2013, Xilinx, Michal Simek 4 * 5 * (C) Copyright 2012 6 * Joe Hershberger <joe.hershberger (at) ni.com> 7 */ 8 9 #include <common.h> 10 #include <console.h> 11 #include <asm/io.h> 12 #include <fs.h> 13 #include <zynqpl.h> 14 #include <linux/sizes.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/sys_proto.h> 17 18 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 19 #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000 20 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 21 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 22 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000 23 #define DEVCFG_ISR_DMA_DONE 0x00002000 24 #define DEVCFG_ISR_PCFG_DONE 0x00000004 25 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000 26 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 27 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 28 #define DEVCFG_STATUS_PCFG_INIT 0x00000010 29 #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010 30 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 31 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 32 33 #ifndef CONFIG_SYS_FPGA_WAIT 34 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ 35 #endif 36 37 #ifndef CONFIG_SYS_FPGA_PROG_TIME 38 #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ 39 #endif 40 41 #define DUMMY_WORD 0xffffffff 42 43 /* Xilinx binary format header */ 44 static const u32 bin_format[] = { 45 DUMMY_WORD, /* Dummy words */ 46 DUMMY_WORD, 47 DUMMY_WORD, 48 DUMMY_WORD, 49 DUMMY_WORD, 50 DUMMY_WORD, 51 DUMMY_WORD, 52 DUMMY_WORD, 53 0x000000bb, /* Sync word */ 54 0x11220044, /* Sync word */ 55 DUMMY_WORD, 56 DUMMY_WORD, 57 0xaa995566, /* Sync word */ 58 }; 59 60 #define SWAP_NO 1 61 #define SWAP_DONE 2 62 63 /* 64 * Load the whole word from unaligned buffer 65 * Keep in your mind that it is byte loading on little-endian system 66 */ 67 static u32 load_word(const void *buf, u32 swap) 68 { 69 u32 word = 0; 70 u8 *bitc = (u8 *)buf; 71 int p; 72 73 if (swap == SWAP_NO) { 74 for (p = 0; p < 4; p++) { 75 word <<= 8; 76 word |= bitc[p]; 77 } 78 } else { 79 for (p = 3; p >= 0; p--) { 80 word <<= 8; 81 word |= bitc[p]; 82 } 83 } 84 85 return word; 86 } 87 88 static u32 check_header(const void *buf) 89 { 90 u32 i, pattern; 91 int swap = SWAP_NO; 92 u32 *test = (u32 *)buf; 93 94 debug("%s: Let's check bitstream header\n", __func__); 95 96 /* Checking that passing bin is not a bitstream */ 97 for (i = 0; i < ARRAY_SIZE(bin_format); i++) { 98 pattern = load_word(&test[i], swap); 99 100 /* 101 * Bitstreams in binary format are swapped 102 * compare to regular bistream. 103 * Do not swap dummy word but if swap is done assume 104 * that parsing buffer is binary format 105 */ 106 if ((__swab32(pattern) != DUMMY_WORD) && 107 (__swab32(pattern) == bin_format[i])) { 108 pattern = __swab32(pattern); 109 swap = SWAP_DONE; 110 debug("%s: data swapped - let's swap\n", __func__); 111 } 112 113 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i, 114 (u32)&test[i], pattern, bin_format[i]); 115 if (pattern != bin_format[i]) { 116 debug("%s: Bitstream is not recognized\n", __func__); 117 return 0; 118 } 119 } 120 debug("%s: Found bitstream header at %x %s swapinng\n", __func__, 121 (u32)buf, swap == SWAP_NO ? "without" : "with"); 122 123 return swap; 124 } 125 126 static void *check_data(u8 *buf, size_t bsize, u32 *swap) 127 { 128 u32 word, p = 0; /* possition */ 129 130 /* Because buf doesn't need to be aligned let's read it by chars */ 131 for (p = 0; p < bsize; p++) { 132 word = load_word(&buf[p], SWAP_NO); 133 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]); 134 135 /* Find the first bitstream dummy word */ 136 if (word == DUMMY_WORD) { 137 debug("%s: Found dummy word at position %x/%x\n", 138 __func__, p, (u32)&buf[p]); 139 *swap = check_header(&buf[p]); 140 if (*swap) { 141 /* FIXME add full bitstream checking here */ 142 return &buf[p]; 143 } 144 } 145 /* Loop can be huge - support CTRL + C */ 146 if (ctrlc()) 147 return NULL; 148 } 149 return NULL; 150 } 151 152 static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) 153 { 154 unsigned long ts; 155 u32 isr_status; 156 157 /* Set up the transfer */ 158 writel((u32)srcbuf, &devcfg_base->dma_src_addr); 159 writel(dstbuf, &devcfg_base->dma_dst_addr); 160 writel(srclen, &devcfg_base->dma_src_len); 161 writel(dstlen, &devcfg_base->dma_dst_len); 162 163 isr_status = readl(&devcfg_base->int_sts); 164 165 /* Polling the PCAP_INIT status for Set */ 166 ts = get_timer(0); 167 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { 168 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { 169 debug("%s: Error: isr = 0x%08X\n", __func__, 170 isr_status); 171 debug("%s: Write count = 0x%08X\n", __func__, 172 readl(&devcfg_base->write_count)); 173 debug("%s: Read count = 0x%08X\n", __func__, 174 readl(&devcfg_base->read_count)); 175 176 return FPGA_FAIL; 177 } 178 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { 179 printf("%s: Timeout wait for DMA to complete\n", 180 __func__); 181 return FPGA_FAIL; 182 } 183 isr_status = readl(&devcfg_base->int_sts); 184 } 185 186 debug("%s: DMA transfer is done\n", __func__); 187 188 /* Clear out the DMA status */ 189 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); 190 191 return FPGA_SUCCESS; 192 } 193 194 static int zynq_dma_xfer_init(bitstream_type bstype) 195 { 196 u32 status, control, isr_status; 197 unsigned long ts; 198 199 /* Clear loopback bit */ 200 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); 201 202 if (bstype != BIT_PARTIAL) { 203 zynq_slcr_devcfg_disable(); 204 205 /* Setting PCFG_PROG_B signal to high */ 206 control = readl(&devcfg_base->ctrl); 207 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 208 209 /* 210 * Delay is required if AES efuse is selected as 211 * key source. 212 */ 213 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) 214 mdelay(5); 215 216 /* Setting PCFG_PROG_B signal to low */ 217 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 218 219 /* 220 * Delay is required if AES efuse is selected as 221 * key source. 222 */ 223 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK) 224 mdelay(5); 225 226 /* Polling the PCAP_INIT status for Reset */ 227 ts = get_timer(0); 228 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { 229 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 230 printf("%s: Timeout wait for INIT to clear\n", 231 __func__); 232 return FPGA_FAIL; 233 } 234 } 235 236 /* Setting PCFG_PROG_B signal to high */ 237 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); 238 239 /* Polling the PCAP_INIT status for Set */ 240 ts = get_timer(0); 241 while (!(readl(&devcfg_base->status) & 242 DEVCFG_STATUS_PCFG_INIT)) { 243 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 244 printf("%s: Timeout wait for INIT to set\n", 245 __func__); 246 return FPGA_FAIL; 247 } 248 } 249 } 250 251 isr_status = readl(&devcfg_base->int_sts); 252 253 /* Clear it all, so if Boot ROM comes back, it can proceed */ 254 writel(0xFFFFFFFF, &devcfg_base->int_sts); 255 256 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) { 257 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status); 258 259 /* If RX FIFO overflow, need to flush RX FIFO first */ 260 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) { 261 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl); 262 writel(0xFFFFFFFF, &devcfg_base->int_sts); 263 } 264 return FPGA_FAIL; 265 } 266 267 status = readl(&devcfg_base->status); 268 269 debug("%s: Status = 0x%08X\n", __func__, status); 270 271 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) { 272 debug("%s: Error: device busy\n", __func__); 273 return FPGA_FAIL; 274 } 275 276 debug("%s: Device ready\n", __func__); 277 278 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) { 279 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) { 280 /* Error state, transfer cannot occur */ 281 debug("%s: ISR indicates error\n", __func__); 282 return FPGA_FAIL; 283 } else { 284 /* Clear out the status */ 285 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); 286 } 287 } 288 289 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) { 290 /* Clear the count of completed DMA transfers */ 291 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); 292 } 293 294 return FPGA_SUCCESS; 295 } 296 297 static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) 298 { 299 u32 *new_buf; 300 u32 i; 301 302 if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { 303 new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); 304 305 /* 306 * This might be dangerous but permits to flash if 307 * ARCH_DMA_MINALIGN is greater than header size 308 */ 309 if (new_buf > buf) { 310 debug("%s: Aligned buffer is after buffer start\n", 311 __func__); 312 new_buf -= ARCH_DMA_MINALIGN; 313 } 314 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, 315 (u32)buf, (u32)new_buf, swap); 316 317 for (i = 0; i < (len/4); i++) 318 new_buf[i] = load_word(&buf[i], swap); 319 320 buf = new_buf; 321 } else if (swap != SWAP_DONE) { 322 /* For bitstream which are aligned */ 323 u32 *new_buf = (u32 *)buf; 324 325 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, 326 swap); 327 328 for (i = 0; i < (len/4); i++) 329 new_buf[i] = load_word(&buf[i], swap); 330 } 331 332 return buf; 333 } 334 335 static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, 336 size_t bsize, u32 blocksize, u32 *swap, 337 bitstream_type *bstype) 338 { 339 u32 *buf_start; 340 u32 diff; 341 342 buf_start = check_data((u8 *)buf, blocksize, swap); 343 344 if (!buf_start) 345 return FPGA_FAIL; 346 347 /* Check if data is postpone from start */ 348 diff = (u32)buf_start - (u32)buf; 349 if (diff) { 350 printf("%s: Bitstream is not validated yet (diff %x)\n", 351 __func__, diff); 352 return FPGA_FAIL; 353 } 354 355 if ((u32)buf < SZ_1M) { 356 printf("%s: Bitstream has to be placed up to 1MB (%x)\n", 357 __func__, (u32)buf); 358 return FPGA_FAIL; 359 } 360 361 if (zynq_dma_xfer_init(*bstype)) 362 return FPGA_FAIL; 363 364 return 0; 365 } 366 367 static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, 368 bitstream_type bstype) 369 { 370 unsigned long ts; /* Timestamp */ 371 u32 isr_status, swap; 372 373 /* 374 * send bsize inplace of blocksize as it was not a bitstream 375 * in chunks 376 */ 377 if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, 378 &bstype)) 379 return FPGA_FAIL; 380 381 buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); 382 383 debug("%s: Source = 0x%08X\n", __func__, (u32)buf); 384 debug("%s: Size = %zu\n", __func__, bsize); 385 386 /* flush(clean & invalidate) d-cache range buf */ 387 flush_dcache_range((u32)buf, (u32)buf + 388 roundup(bsize, ARCH_DMA_MINALIGN)); 389 390 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) 391 return FPGA_FAIL; 392 393 isr_status = readl(&devcfg_base->int_sts); 394 /* Check FPGA configuration completion */ 395 ts = get_timer(0); 396 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { 397 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 398 printf("%s: Timeout wait for FPGA to config\n", 399 __func__); 400 return FPGA_FAIL; 401 } 402 isr_status = readl(&devcfg_base->int_sts); 403 } 404 405 debug("%s: FPGA config done\n", __func__); 406 407 if (bstype != BIT_PARTIAL) 408 zynq_slcr_devcfg_enable(); 409 410 return FPGA_SUCCESS; 411 } 412 413 #if defined(CONFIG_CMD_FPGA_LOADFS) 414 static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, 415 fpga_fs_info *fsinfo) 416 { 417 unsigned long ts; /* Timestamp */ 418 u32 isr_status, swap; 419 u32 partialbit = 0; 420 loff_t blocksize, actread; 421 loff_t pos = 0; 422 int fstype; 423 char *interface, *dev_part, *filename; 424 425 blocksize = fsinfo->blocksize; 426 interface = fsinfo->interface; 427 dev_part = fsinfo->dev_part; 428 filename = fsinfo->filename; 429 fstype = fsinfo->fstype; 430 431 if (fs_set_blk_dev(interface, dev_part, fstype)) 432 return FPGA_FAIL; 433 434 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0) 435 return FPGA_FAIL; 436 437 if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap, 438 &partialbit)) 439 return FPGA_FAIL; 440 441 dcache_disable(); 442 443 do { 444 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); 445 446 if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2, 447 0xffffffff, 0)) 448 return FPGA_FAIL; 449 450 bsize -= blocksize; 451 pos += blocksize; 452 453 if (fs_set_blk_dev(interface, dev_part, fstype)) 454 return FPGA_FAIL; 455 456 if (bsize > blocksize) { 457 if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0) 458 return FPGA_FAIL; 459 } else { 460 if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0) 461 return FPGA_FAIL; 462 } 463 } while (bsize > blocksize); 464 465 buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap); 466 467 if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) 468 return FPGA_FAIL; 469 470 dcache_enable(); 471 472 isr_status = readl(&devcfg_base->int_sts); 473 474 /* Check FPGA configuration completion */ 475 ts = get_timer(0); 476 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { 477 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { 478 printf("%s: Timeout wait for FPGA to config\n", 479 __func__); 480 return FPGA_FAIL; 481 } 482 isr_status = readl(&devcfg_base->int_sts); 483 } 484 485 debug("%s: FPGA config done\n", __func__); 486 487 if (!partialbit) 488 zynq_slcr_devcfg_enable(); 489 490 return FPGA_SUCCESS; 491 } 492 #endif 493 494 struct xilinx_fpga_op zynq_op = { 495 .load = zynq_load, 496 #if defined(CONFIG_CMD_FPGA_LOADFS) 497 .loadfs = zynq_loadfs, 498 #endif 499 }; 500
