/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
MipsGenAsmWriter.inc | [all...] |
MipsGenRegisterInfo.inc | 199 FCC0 = 179, [all...] |
MipsGenAsmMatcher.inc | [all...] |
MipsGenInstrInfo.inc | [all...] |
/external/swiftshader/third_party/subzero/src/ |
IceAssemblerMIPS32.cpp | 443 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, 449 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, 455 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, 461 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, 467 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, 473 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, 479 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, 485 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, 491 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, 497 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0, [all...] |
IceTargetLoweringMIPS32.cpp | [all...] |
IceInstMIPS32.h | 80 using FCC = enum { FCC0 = 0, FCC1, FCC2, FCC3, FCC4, FCC5, FCC6, FCC7 }; [all...] |
/external/llvm/lib/Target/Mips/InstPrinter/ |
MipsInstPrinter.cpp | 248 // bc1t $fcc0, $L1 => bc1t $L1 249 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); 251 // bc1f $fcc0, $L1 => bc1f $L1 252 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/InstPrinter/ |
MipsInstPrinter.cpp | 243 // bc1t $fcc0, $L1 => bc1t $L1 244 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); 246 // bc1f $fcc0, $L1 => bc1f $L1 247 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
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/external/llvm/lib/Target/Sparc/InstPrinter/ |
SparcInstPrinter.cpp | 88 || (MI->getOperand(0).getReg() != SP::FCC0)) 90 // if V8, skip printing %fcc0.
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/InstPrinter/ |
SparcInstPrinter.cpp | 88 || (MI->getOperand(0).getReg() != SP::FCC0)) 90 // if V8, skip printing %fcc0.
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/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 570 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 573 True.getValueType(), True, FCC0, False, Cond); [all...] |
MipsFastISel.cpp | 707 Mips::FCC0, RegState::ImplicitDefine); 710 .addReg(Mips::FCC0) [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 665 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 668 True.getValueType(), True, FCC0, False, Cond); [all...] |
MipsFastISel.cpp | 743 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) 747 .addReg(Mips::FCC0) [all...] |
/external/llvm/lib/Target/Sparc/Disassembler/ |
SparcDisassembler.cpp | 108 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/Disassembler/ |
SparcDisassembler.cpp | 110 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
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/external/llvm/lib/Target/Sparc/AsmParser/ |
SparcAsmParser.cpp | 1033 // %fcc0 - %fcc3 1038 RegNo = Sparc::FCC0 + intVal; [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/AsmParser/ |
SparcAsmParser.cpp | 1023 // %fcc0 - %fcc3 1028 RegNo = Sparc::FCC0 + intVal; [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | 526 /// True if all of $fcc0 - $fcc7 exist for the current ISA. [all...] |