1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the Sparc Disassembler. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Sparc.h" 15 #include "SparcRegisterInfo.h" 16 #include "SparcSubtarget.h" 17 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 18 #include "llvm/MC/MCFixedLenDisassembler.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCAsmInfo.h" 22 #include "llvm/Support/TargetRegistry.h" 23 24 using namespace llvm; 25 26 #define DEBUG_TYPE "sparc-disassembler" 27 28 typedef MCDisassembler::DecodeStatus DecodeStatus; 29 30 namespace { 31 32 /// A disassembler class for Sparc. 33 class SparcDisassembler : public MCDisassembler { 34 public: 35 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) 36 : MCDisassembler(STI, Ctx) {} 37 virtual ~SparcDisassembler() {} 38 39 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 40 ArrayRef<uint8_t> Bytes, uint64_t Address, 41 raw_ostream &VStream, 42 raw_ostream &CStream) const override; 43 }; 44 } 45 46 namespace llvm { 47 extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget; 48 } 49 50 static MCDisassembler *createSparcDisassembler(const Target &T, 51 const MCSubtargetInfo &STI, 52 MCContext &Ctx) { 53 return new SparcDisassembler(STI, Ctx); 54 } 55 56 57 extern "C" void LLVMInitializeSparcDisassembler() { 58 // Register the disassembler. 59 TargetRegistry::RegisterMCDisassembler(TheSparcTarget, 60 createSparcDisassembler); 61 TargetRegistry::RegisterMCDisassembler(TheSparcV9Target, 62 createSparcDisassembler); 63 TargetRegistry::RegisterMCDisassembler(TheSparcelTarget, 64 createSparcDisassembler); 65 } 66 67 static const unsigned IntRegDecoderTable[] = { 68 SP::G0, SP::G1, SP::G2, SP::G3, 69 SP::G4, SP::G5, SP::G6, SP::G7, 70 SP::O0, SP::O1, SP::O2, SP::O3, 71 SP::O4, SP::O5, SP::O6, SP::O7, 72 SP::L0, SP::L1, SP::L2, SP::L3, 73 SP::L4, SP::L5, SP::L6, SP::L7, 74 SP::I0, SP::I1, SP::I2, SP::I3, 75 SP::I4, SP::I5, SP::I6, SP::I7 }; 76 77 static const unsigned FPRegDecoderTable[] = { 78 SP::F0, SP::F1, SP::F2, SP::F3, 79 SP::F4, SP::F5, SP::F6, SP::F7, 80 SP::F8, SP::F9, SP::F10, SP::F11, 81 SP::F12, SP::F13, SP::F14, SP::F15, 82 SP::F16, SP::F17, SP::F18, SP::F19, 83 SP::F20, SP::F21, SP::F22, SP::F23, 84 SP::F24, SP::F25, SP::F26, SP::F27, 85 SP::F28, SP::F29, SP::F30, SP::F31 }; 86 87 static const unsigned DFPRegDecoderTable[] = { 88 SP::D0, SP::D16, SP::D1, SP::D17, 89 SP::D2, SP::D18, SP::D3, SP::D19, 90 SP::D4, SP::D20, SP::D5, SP::D21, 91 SP::D6, SP::D22, SP::D7, SP::D23, 92 SP::D8, SP::D24, SP::D9, SP::D25, 93 SP::D10, SP::D26, SP::D11, SP::D27, 94 SP::D12, SP::D28, SP::D13, SP::D29, 95 SP::D14, SP::D30, SP::D15, SP::D31 }; 96 97 static const unsigned QFPRegDecoderTable[] = { 98 SP::Q0, SP::Q8, ~0U, ~0U, 99 SP::Q1, SP::Q9, ~0U, ~0U, 100 SP::Q2, SP::Q10, ~0U, ~0U, 101 SP::Q3, SP::Q11, ~0U, ~0U, 102 SP::Q4, SP::Q12, ~0U, ~0U, 103 SP::Q5, SP::Q13, ~0U, ~0U, 104 SP::Q6, SP::Q14, ~0U, ~0U, 105 SP::Q7, SP::Q15, ~0U, ~0U } ; 106 107 static const unsigned FCCRegDecoderTable[] = { 108 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 }; 109 110 static const unsigned ASRRegDecoderTable[] = { 111 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, 112 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, 113 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, 114 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, 115 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, 116 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, 117 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, 118 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31}; 119 120 static const unsigned PRRegDecoderTable[] = { 121 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE, 122 SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, 123 SP::OTHERWIN, SP::WSTATE 124 }; 125 126 static const uint16_t IntPairDecoderTable[] = { 127 SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7, 128 SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7, 129 SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7, 130 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7, 131 }; 132 133 static const unsigned CPRegDecoderTable[] = { 134 SP::C0, SP::C1, SP::C2, SP::C3, 135 SP::C4, SP::C5, SP::C6, SP::C7, 136 SP::C8, SP::C9, SP::C10, SP::C11, 137 SP::C12, SP::C13, SP::C14, SP::C15, 138 SP::C16, SP::C17, SP::C18, SP::C19, 139 SP::C20, SP::C21, SP::C22, SP::C23, 140 SP::C24, SP::C25, SP::C26, SP::C27, 141 SP::C28, SP::C29, SP::C30, SP::C31 142 }; 143 144 145 static const uint16_t CPPairDecoderTable[] = { 146 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7, 147 SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15, 148 SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23, 149 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31 150 }; 151 152 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, 153 unsigned RegNo, 154 uint64_t Address, 155 const void *Decoder) { 156 if (RegNo > 31) 157 return MCDisassembler::Fail; 158 unsigned Reg = IntRegDecoderTable[RegNo]; 159 Inst.addOperand(MCOperand::createReg(Reg)); 160 return MCDisassembler::Success; 161 } 162 163 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, 164 unsigned RegNo, 165 uint64_t Address, 166 const void *Decoder) { 167 if (RegNo > 31) 168 return MCDisassembler::Fail; 169 unsigned Reg = IntRegDecoderTable[RegNo]; 170 Inst.addOperand(MCOperand::createReg(Reg)); 171 return MCDisassembler::Success; 172 } 173 174 175 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, 176 unsigned RegNo, 177 uint64_t Address, 178 const void *Decoder) { 179 if (RegNo > 31) 180 return MCDisassembler::Fail; 181 unsigned Reg = FPRegDecoderTable[RegNo]; 182 Inst.addOperand(MCOperand::createReg(Reg)); 183 return MCDisassembler::Success; 184 } 185 186 187 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, 188 unsigned RegNo, 189 uint64_t Address, 190 const void *Decoder) { 191 if (RegNo > 31) 192 return MCDisassembler::Fail; 193 unsigned Reg = DFPRegDecoderTable[RegNo]; 194 Inst.addOperand(MCOperand::createReg(Reg)); 195 return MCDisassembler::Success; 196 } 197 198 199 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, 200 unsigned RegNo, 201 uint64_t Address, 202 const void *Decoder) { 203 if (RegNo > 31) 204 return MCDisassembler::Fail; 205 206 unsigned Reg = QFPRegDecoderTable[RegNo]; 207 if (Reg == ~0U) 208 return MCDisassembler::Fail; 209 Inst.addOperand(MCOperand::createReg(Reg)); 210 return MCDisassembler::Success; 211 } 212 213 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst, 214 unsigned RegNo, 215 uint64_t Address, 216 const void *Decoder) { 217 if (RegNo > 31) 218 return MCDisassembler::Fail; 219 unsigned Reg = CPRegDecoderTable[RegNo]; 220 Inst.addOperand(MCOperand::createReg(Reg)); 221 return MCDisassembler::Success; 222 } 223 224 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, 225 uint64_t Address, 226 const void *Decoder) { 227 if (RegNo > 3) 228 return MCDisassembler::Fail; 229 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); 230 return MCDisassembler::Success; 231 } 232 233 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, 234 uint64_t Address, 235 const void *Decoder) { 236 if (RegNo > 31) 237 return MCDisassembler::Fail; 238 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); 239 return MCDisassembler::Success; 240 } 241 242 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, 243 uint64_t Address, 244 const void *Decoder) { 245 if (RegNo >= array_lengthof(PRRegDecoderTable)) 246 return MCDisassembler::Fail; 247 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); 248 return MCDisassembler::Success; 249 } 250 251 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo, 252 uint64_t Address, const void *Decoder) { 253 DecodeStatus S = MCDisassembler::Success; 254 255 if (RegNo > 31) 256 return MCDisassembler::Fail; 257 258 if ((RegNo & 1)) 259 S = MCDisassembler::SoftFail; 260 261 unsigned RegisterPair = IntPairDecoderTable[RegNo/2]; 262 Inst.addOperand(MCOperand::createReg(RegisterPair)); 263 return S; 264 } 265 266 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo, 267 uint64_t Address, const void *Decoder) { 268 if (RegNo > 31) 269 return MCDisassembler::Fail; 270 271 unsigned RegisterPair = CPPairDecoderTable[RegNo/2]; 272 Inst.addOperand(MCOperand::createReg(RegisterPair)); 273 return MCDisassembler::Success; 274 } 275 276 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, 277 const void *Decoder); 278 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, 279 const void *Decoder); 280 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, 281 const void *Decoder); 282 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, 283 const void *Decoder); 284 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, 285 const void *Decoder); 286 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, 287 const void *Decoder); 288 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, 289 const void *Decoder); 290 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, 291 uint64_t Address, const void *Decoder); 292 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, 293 uint64_t Address, const void *Decoder); 294 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, 295 uint64_t Address, const void *Decoder); 296 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, 297 uint64_t Address, const void *Decoder); 298 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, 299 uint64_t Address, const void *Decoder); 300 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, 301 uint64_t Address, const void *Decoder); 302 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, 303 uint64_t Address, const void *Decoder); 304 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn, 305 uint64_t Address, const void *Decoder); 306 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn, 307 uint64_t Address, const void *Decoder); 308 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, 309 const void *Decoder); 310 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 311 const void *Decoder); 312 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, 313 const void *Decoder); 314 static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address, 315 const void *Decoder); 316 317 #include "SparcGenDisassemblerTables.inc" 318 319 /// Read four bytes from the ArrayRef and return 32 bit word. 320 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, 321 uint64_t &Size, uint32_t &Insn, 322 bool IsLittleEndian) { 323 // We want to read exactly 4 Bytes of data. 324 if (Bytes.size() < 4) { 325 Size = 0; 326 return MCDisassembler::Fail; 327 } 328 329 Insn = IsLittleEndian 330 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | 331 (Bytes[3] << 24) 332 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | 333 (Bytes[0] << 24); 334 335 return MCDisassembler::Success; 336 } 337 338 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, 339 ArrayRef<uint8_t> Bytes, 340 uint64_t Address, 341 raw_ostream &VStream, 342 raw_ostream &CStream) const { 343 uint32_t Insn; 344 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); 345 DecodeStatus Result = 346 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian); 347 if (Result == MCDisassembler::Fail) 348 return MCDisassembler::Fail; 349 350 // Calling the auto-generated decoder function. 351 352 if (STI.getFeatureBits()[Sparc::FeatureV9]) 353 { 354 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI); 355 } 356 else 357 { 358 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI); 359 } 360 if (Result != MCDisassembler::Fail) 361 return Result; 362 363 Result = 364 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); 365 366 if (Result != MCDisassembler::Fail) { 367 Size = 4; 368 return Result; 369 } 370 371 return MCDisassembler::Fail; 372 } 373 374 375 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, 376 const void *Decoder); 377 378 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, 379 const void *Decoder, 380 bool isLoad, DecodeFunc DecodeRD) { 381 unsigned rd = fieldFromInstruction(insn, 25, 5); 382 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 383 bool isImm = fieldFromInstruction(insn, 13, 1); 384 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) 385 unsigned asi = fieldFromInstruction(insn, 5, 8); 386 unsigned rs2 = 0; 387 unsigned simm13 = 0; 388 if (isImm) 389 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 390 else 391 rs2 = fieldFromInstruction(insn, 0, 5); 392 393 DecodeStatus status; 394 if (isLoad) { 395 status = DecodeRD(MI, rd, Address, Decoder); 396 if (status != MCDisassembler::Success) 397 return status; 398 } 399 400 // Decode rs1. 401 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 402 if (status != MCDisassembler::Success) 403 return status; 404 405 // Decode imm|rs2. 406 if (isImm) 407 MI.addOperand(MCOperand::createImm(simm13)); 408 else { 409 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 410 if (status != MCDisassembler::Success) 411 return status; 412 } 413 414 if (hasAsi) 415 MI.addOperand(MCOperand::createImm(asi)); 416 417 if (!isLoad) { 418 status = DecodeRD(MI, rd, Address, Decoder); 419 if (status != MCDisassembler::Success) 420 return status; 421 } 422 return MCDisassembler::Success; 423 } 424 425 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address, 426 const void *Decoder) { 427 return DecodeMem(Inst, insn, Address, Decoder, true, 428 DecodeIntRegsRegisterClass); 429 } 430 431 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address, 432 const void *Decoder) { 433 return DecodeMem(Inst, insn, Address, Decoder, true, 434 DecodeIntPairRegisterClass); 435 } 436 437 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address, 438 const void *Decoder) { 439 return DecodeMem(Inst, insn, Address, Decoder, true, 440 DecodeFPRegsRegisterClass); 441 } 442 443 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address, 444 const void *Decoder) { 445 return DecodeMem(Inst, insn, Address, Decoder, true, 446 DecodeDFPRegsRegisterClass); 447 } 448 449 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address, 450 const void *Decoder) { 451 return DecodeMem(Inst, insn, Address, Decoder, true, 452 DecodeQFPRegsRegisterClass); 453 } 454 455 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address, 456 const void *Decoder) { 457 return DecodeMem(Inst, insn, Address, Decoder, true, 458 DecodeCPRegsRegisterClass); 459 } 460 461 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address, 462 const void *Decoder) { 463 return DecodeMem(Inst, insn, Address, Decoder, true, 464 DecodeCPPairRegisterClass); 465 } 466 467 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn, 468 uint64_t Address, const void *Decoder) { 469 return DecodeMem(Inst, insn, Address, Decoder, false, 470 DecodeIntRegsRegisterClass); 471 } 472 473 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn, 474 uint64_t Address, const void *Decoder) { 475 return DecodeMem(Inst, insn, Address, Decoder, false, 476 DecodeIntPairRegisterClass); 477 } 478 479 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address, 480 const void *Decoder) { 481 return DecodeMem(Inst, insn, Address, Decoder, false, 482 DecodeFPRegsRegisterClass); 483 } 484 485 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn, 486 uint64_t Address, const void *Decoder) { 487 return DecodeMem(Inst, insn, Address, Decoder, false, 488 DecodeDFPRegsRegisterClass); 489 } 490 491 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn, 492 uint64_t Address, const void *Decoder) { 493 return DecodeMem(Inst, insn, Address, Decoder, false, 494 DecodeQFPRegsRegisterClass); 495 } 496 497 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn, 498 uint64_t Address, const void *Decoder) { 499 return DecodeMem(Inst, insn, Address, Decoder, false, 500 DecodeCPRegsRegisterClass); 501 } 502 503 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn, 504 uint64_t Address, const void *Decoder) { 505 return DecodeMem(Inst, insn, Address, Decoder, false, 506 DecodeCPPairRegisterClass); 507 } 508 509 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch, 510 uint64_t Address, uint64_t Offset, 511 uint64_t Width, MCInst &MI, 512 const void *Decoder) { 513 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 514 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, 515 Offset, Width); 516 } 517 518 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, 519 uint64_t Address, const void *Decoder) { 520 unsigned tgt = fieldFromInstruction(insn, 0, 30); 521 tgt <<= 2; 522 if (!tryAddingSymbolicOperand(tgt+Address, false, Address, 523 0, 30, MI, Decoder)) 524 MI.addOperand(MCOperand::createImm(tgt)); 525 return MCDisassembler::Success; 526 } 527 528 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, 529 uint64_t Address, const void *Decoder) { 530 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 531 MI.addOperand(MCOperand::createImm(tgt)); 532 return MCDisassembler::Success; 533 } 534 535 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, 536 const void *Decoder) { 537 538 unsigned rd = fieldFromInstruction(insn, 25, 5); 539 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 540 unsigned isImm = fieldFromInstruction(insn, 13, 1); 541 unsigned rs2 = 0; 542 unsigned simm13 = 0; 543 if (isImm) 544 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 545 else 546 rs2 = fieldFromInstruction(insn, 0, 5); 547 548 // Decode RD. 549 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); 550 if (status != MCDisassembler::Success) 551 return status; 552 553 // Decode RS1. 554 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 555 if (status != MCDisassembler::Success) 556 return status; 557 558 // Decode RS1 | SIMM13. 559 if (isImm) 560 MI.addOperand(MCOperand::createImm(simm13)); 561 else { 562 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 563 if (status != MCDisassembler::Success) 564 return status; 565 } 566 return MCDisassembler::Success; 567 } 568 569 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, 570 const void *Decoder) { 571 572 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 573 unsigned isImm = fieldFromInstruction(insn, 13, 1); 574 unsigned rs2 = 0; 575 unsigned simm13 = 0; 576 if (isImm) 577 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 578 else 579 rs2 = fieldFromInstruction(insn, 0, 5); 580 581 // Decode RS1. 582 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 583 if (status != MCDisassembler::Success) 584 return status; 585 586 // Decode RS2 | SIMM13. 587 if (isImm) 588 MI.addOperand(MCOperand::createImm(simm13)); 589 else { 590 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 591 if (status != MCDisassembler::Success) 592 return status; 593 } 594 return MCDisassembler::Success; 595 } 596 597 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, 598 const void *Decoder) { 599 600 unsigned rd = fieldFromInstruction(insn, 25, 5); 601 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 602 unsigned isImm = fieldFromInstruction(insn, 13, 1); 603 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) 604 unsigned asi = fieldFromInstruction(insn, 5, 8); 605 unsigned rs2 = 0; 606 unsigned simm13 = 0; 607 if (isImm) 608 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); 609 else 610 rs2 = fieldFromInstruction(insn, 0, 5); 611 612 // Decode RD. 613 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); 614 if (status != MCDisassembler::Success) 615 return status; 616 617 // Decode RS1. 618 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 619 if (status != MCDisassembler::Success) 620 return status; 621 622 // Decode RS1 | SIMM13. 623 if (isImm) 624 MI.addOperand(MCOperand::createImm(simm13)); 625 else { 626 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 627 if (status != MCDisassembler::Success) 628 return status; 629 } 630 631 if (hasAsi) 632 MI.addOperand(MCOperand::createImm(asi)); 633 634 return MCDisassembler::Success; 635 } 636 637 static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address, 638 const void *Decoder) { 639 640 unsigned rs1 = fieldFromInstruction(insn, 14, 5); 641 unsigned isImm = fieldFromInstruction(insn, 13, 1); 642 unsigned cc =fieldFromInstruction(insn, 25, 4); 643 unsigned rs2 = 0; 644 unsigned imm7 = 0; 645 if (isImm) 646 imm7 = fieldFromInstruction(insn, 0, 7); 647 else 648 rs2 = fieldFromInstruction(insn, 0, 5); 649 650 // Decode RS1. 651 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); 652 if (status != MCDisassembler::Success) 653 return status; 654 655 // Decode RS1 | IMM7. 656 if (isImm) 657 MI.addOperand(MCOperand::createImm(imm7)); 658 else { 659 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); 660 if (status != MCDisassembler::Success) 661 return status; 662 } 663 664 // Decode CC 665 MI.addOperand(MCOperand::createImm(cc)); 666 667 return MCDisassembler::Success; 668 } 669
