| /external/skia/src/core/ |
| SkCpu.h | 23 FMA = 1 << 8,
28 HSW = AVX2 | BMI1 | BMI2 | F16C | FMA,
87 // FMA doesn't fit neatly into this total ordering.
89 // TODO: circle back on this if we find ourselves limited by lack of compile-time FMA
|
| SkCpu.cpp | 52 if (abcd[2] & (1<<12)) { features |= SkCpu:: FMA; }
|
| /external/skqp/src/core/ |
| SkCpu.h | 23 FMA = 1 << 8,
28 HSW = AVX2 | BMI1 | BMI2 | F16C | FMA,
87 // FMA doesn't fit neatly into this total ordering.
89 // TODO: circle back on this if we find ourselves limited by lack of compile-time FMA
|
| SkCpu.cpp | 52 if (abcd[2] & (1<<12)) { features |= SkCpu:: FMA; }
|
| /external/tensorflow/tensorflow/core/platform/ |
| cpu_info.h | 73 FMA = 15,
|
| cpu_feature_guard.cc | 87 CheckFeatureOrDie(CPUFeature::FMA, "FMA");
137 CheckIfFeatureUnused(CPUFeature::FMA, "FMA", missing_instructions);
|
| cpu_info.cc | 230 case FMA: return cpuid->have_fma_;
|
| /external/tensorflow/tensorflow/core/kernels/ |
| sparse_matmul_op.cc | 283 #define FMA(a, b, c, d) d = Eigen::internal::pmadd<Packet>(a, b, c);
418 FMA(a, b_0, c1, c1);
419 FMA(a, b_1, c2, c2);
446 FMA(a1, b1_0, c1, c1);
447 FMA(a1, b1_1, c2, c2);
448 FMA(a2, b2_0, c1, c1);
449 FMA(a2, b2_1, c2, c2);
450 FMA(a3, b3_0, c1, c1);
451 FMA(a3, b3_1, c2, c2);
490 FMA(a1, b1_0, c1, c1)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| AMDGPUSubtarget.h | 335 bool FMA;
517 return FMA;
959 bool FMA;
1048 bool hasFMA() const { return FMA; }
|
| SIISelLowering.cpp | 473 setOperationAction(ISD::FMA, MVT::f16, Legal);
568 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
626 setTargetDAGCombine(ISD::FMA);
686 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
[all...] |
| AMDGPUSubtarget.cpp | 453 FMA(false),
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ISDOpcodes.h | 235 FADD, FSUB, FMUL, FMA, FDIV, FREM,
[all...] |
| /external/syzkaller/pkg/ifuzz/generated/ |
| insns.go | [all...] |
| /external/capstone/ |
| config.mk | 47 # - Fused Multiply Add Operations (FMA)
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 243 /// FMA - Perform a * b + c with no intermediate rounding step.
244 FMA,
[all...] |
| BasicTTIImpl.h | 802 case Intrinsic::fma:
803 ISDs.push_back(ISD::FMA);
806 ISDs.push_back(ISD::FMA);
861 // If we can't lower fmuladd into an FMA estimate the cost as a floating
[all...] |
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| isa.hpp | 57 bool FMA(void) { return CPU_Rep.f_1_ECX_[12]; }
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 277 /// FMA - Perform a * b + c with no intermediate rounding step.
278 FMA,
[all...] |
| /external/llvm/test/tools/llvm-readobj/ARM/ |
| attribute-2.s | 37 @CHECK-OBJ-NEXT: Description: NEONv2+FMA
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-readobj/ARM/ |
| attribute-2.s | 37 @CHECK-OBJ-NEXT: Description: NEONv2+FMA
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/ |
| AutoUpgrade.cpp | 78 Name.startswith("fma.vfmadd.") || // Added in 7.0
79 Name.startswith("fma.vfmsub.") || // Added in 7.0
80 Name.startswith("fma.vfmaddsub.") || // Added in 7.0
81 Name.startswith("fma.vfmsubadd.") || // Added in 7.0
82 Name.startswith("fma.vfnmadd.") || // Added in 7.0
83 Name.startswith("fma.vfnmsub.") || // Added in 7.0
[all...] |
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_info_opcodes.h | 20 OPCODE(1, 3, COMP, FMA)
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 146 setOperationAction(ISD::FMA, MVT::f32, Expand);
147 setOperationAction(ISD::FMA, MVT::f64, Expand);
[all...] |
| /device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ |
| Cpuid.h | 240 /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
243 UINT32 FMA:1;
[all...] |
