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    Searched refs:FP_TO_SINT (Results 1 - 25 of 80) sorted by null

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  /external/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 153 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
155 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
157 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
171 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
173 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
175 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
188 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
190 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
192 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
194 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 214 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
216 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
218 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
232 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
234 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
236 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
249 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
251 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
253 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
255 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64TargetTransformInfo.cpp 256 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
257 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
258 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
264 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
265 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
266 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
272 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
273 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
278 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
279 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
AArch64TargetTransformInfo.cpp 359 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
360 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
361 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
367 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
368 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
369 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
375 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
376 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
381 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
382 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }
    [all...]
  /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
ISDOpcodes.h 384 FP_TO_SINT,
    [all...]
  /external/llvm/include/llvm/CodeGen/
ISDOpcodes.h 448 FP_TO_SINT,
    [all...]
  /external/llvm/lib/Target/X86/
X86IntrinsicsInfo.h     [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
ISDOpcodes.h 494 FP_TO_SINT,
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 299 case ISD::FP_TO_SINT:
392 case ISD::FP_TO_SINT:
394 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
478 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
479 NewOpc = ISD::FP_TO_SINT;
    [all...]
LegalizeFloatTypes.cpp     [all...]
LegalizeVectorTypes.cpp 89 case ISD::FP_TO_SINT:
440 case ISD::FP_TO_SINT:
648 case ISD::FP_TO_SINT:
    [all...]
SelectionDAGDumper.cpp 256 case ISD::FP_TO_SINT: return "fp_to_sint";
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 170 case ISD::FP_TO_SINT:
LegalizeFloatTypes.cpp 587 case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break;
734 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
    [all...]
LegalizeVectorTypes.cpp 83 case ISD::FP_TO_SINT:
460 case ISD::FP_TO_SINT:
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 358 case ISD::FP_TO_SINT:
464 case ISD::FP_TO_SINT:
538 // Change FP_TO_UINT to FP_TO_SINT if possible.
541 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
542 NewOpc = ISD::FP_TO_SINT;
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp     [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
SPUISelLowering.cpp 325 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
327 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
331 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
333 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
335 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
383 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
386 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 225 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
372 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
376 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
377 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
501 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
522 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
528 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
653 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 259 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
260 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
370 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
388 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
394 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
515 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
646 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
701 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
751 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal)
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 163 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Custom);
164 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
276 setTargetDAGCombine(ISD::FP_TO_SINT);
662 // Since we don't care about out of bounds values we can use FP_TO_SINT for
666 case ISD::FP_TO_SINT: {
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp     [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/Alpha/
AlphaISelLowering.cpp 86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
629 case ISD::FP_TO_SINT: {
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/Sparc/
SparcISelLowering.cpp 721 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
    [all...]
  /external/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 125 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
196 setTargetDAGCombine(ISD::FP_TO_SINT);
841 // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
843 case ISD::FP_TO_SINT: {
    [all...]

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