1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Watchdog driver for the FTWDT010 Watch Dog Driver 4 * 5 * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com) 6 * Based on sa1100_wdt.c by Oleg Drokin <green (at) crimea.edu> 7 * Based on SoftDog driver by Alan Cox <alan (at) redhat.com> 8 * 9 * Copyright (C) 2011 Andes Technology Corporation 10 * Macpaul Lin, Andes Technology Corporation <macpaul (at) andestech.com> 11 * 12 * 27/11/2004 Initial release, Faraday. 13 * 12/01/2011 Port to u-boot, Macpaul Lin. 14 */ 15 16 #ifndef __FTWDT010_H 17 #define __FTWDT010_H 18 19 struct ftwdt010_wdt { 20 unsigned int wdcounter; /* Counter Reg - 0x00 */ 21 unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */ 22 unsigned int wdrestart; /* Counter Restart Reg - 0x08 */ 23 unsigned int wdcr; /* Control Reg - 0x0c */ 24 unsigned int wdstatus; /* Status Reg - 0x10 */ 25 unsigned int wdclear; /* Timer Clear - 0x14 */ 26 unsigned int wdintrlen; /* Interrupt Length - 0x18 */ 27 }; 28 29 /* 30 * WDLOAD - Counter Auto Reload Register 31 * The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default. 32 * Which means in a 66MHz system, the period of Watch Dog timer reset is 33 * one second. 34 */ 35 #define FTWDT010_WDLOAD(x) ((x) & 0xffffffff) 36 37 /* 38 * WDRESTART - Watch Dog Timer Counter Restart Register 39 * If writing 0x5AB9 to WDRESTART register, Watch Dog timer will 40 * automatically reload WDLOAD to WDCOUNTER and restart counting. 41 */ 42 #define FTWDT010_WDRESTART_MAGIC 0x5AB9 43 44 /* WDCR - Watch Dog Timer Control Register */ 45 #define FTWDT010_WDCR_ENABLE (1 << 0) 46 #define FTWDT010_WDCR_RST (1 << 1) 47 #define FTWDT010_WDCR_INTR (1 << 2) 48 /* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */ 49 #define FTWDT010_WDCR_EXT (1 << 3) 50 /* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK. 51 * The clock source PCLK cannot be gated when system sleeps, even if 52 * WDCLOCK bit is turned on. 53 * 54 * Faraday's Watch Dog timer can be driven by an external clock. The 55 * programmer just needs to write one to WdCR[WdClock] bit. 56 * 57 * Note: There is a limitation between EXTCLK and PCLK: 58 * EXTCLK cycle time / PCLK cycle time > 2. 59 * If the system does not need an external clock, 60 * just keep WdCR[WdClock] bit in its default value. 61 */ 62 #define FTWDT010_WDCR_CLOCK (1 << 4) 63 64 /* 65 * WDSTATUS - Watch Dog Timer Status Register 66 * This bit is set when the counter reaches Zero 67 */ 68 #define FTWDT010_WDSTATUS(x) ((x) & 0x1) 69 70 /* 71 * WDCLEAR - Watch Dog Timer Clear Register 72 * Writing one to this register will clear WDSTATUS. 73 */ 74 #define FTWDT010_WDCLEAR (1 << 0) 75 76 /* 77 * WDINTRLEN - Watch Dog Timer Interrupt Length 78 * This register controls the duration length of wd_rst, wd_intr and wd_ext. 79 * The default value is 0xFF. 80 */ 81 #define FTWDT010_WDINTRLEN(x) ((x) & 0xff) 82 83 /* 84 * Variable timeout should be set in ms. 85 * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms. 86 * WDLOAD = timeout * TIMEOUT_FACTOR. 87 */ 88 #define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */ 89 90 void ftwdt010_wdt_reset(void); 91 void ftwdt010_wdt_disable(void); 92 93 #endif /* __FTWDT010_H */ 94
