| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 382 unsigned FirstReg = 0;
390 if (!FirstReg) FirstReg = R;
393 return FirstReg;
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 223 unsigned FirstReg = 0;
231 if (!FirstReg) FirstReg = R;
234 return FirstReg;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 373 unsigned FirstReg = 0;
381 if (!FirstReg) FirstReg = R;
384 return FirstReg;
|
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 487 unsigned FirstReg = 0;
494 if (FirstReg != 0) {
496 State->UnionGroups(FirstReg, Reg);
499 FirstReg = Reg;
503 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 494 unsigned FirstReg = 0;
501 if (FirstReg != 0) {
503 State->UnionGroups(FirstReg, Reg);
506 FirstReg = Reg;
510 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.cpp | 506 unsigned FirstReg = 0;
513 if (FirstReg != 0) {
515 State->UnionGroups(FirstReg, Reg);
518 FirstReg = Reg;
522 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| MipsISelLowering.h | 468 const Argument *FuncArg, unsigned FirstReg,
477 unsigned FirstReg, unsigned LastReg,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| MipsISelLowering.h | 576 const Argument *FuncArg, unsigned FirstReg,
585 unsigned FirstReg, unsigned LastReg,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
797 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
798 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
800 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
802 unsigned OldFirstReg = FirstReg;
803 FirstReg = MRI.createVirtualRegister(FirstRC);
804 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
809 .addReg(FirstReg).addReg(SecondReg)
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
849 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
850 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
852 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
854 unsigned OldFirstReg = FirstReg;
855 FirstReg = MRI.createVirtualRegister(FirstRC);
856 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
861 .addReg(FirstReg).addReg(SecondReg)
[all...] |
| /external/capstone/arch/AArch64/ |
| AArch64InstPrinter.c | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceTargetLoweringMIPS32.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
