| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| AMDGPUSubtarget.h | 59 GFX9 = 7
501 return getGeneration() >= AMDGPUSubtarget::GFX9;
505 return getGeneration() >= AMDGPUSubtarget::GFX9;
550 return getGeneration() >= AMDGPUSubtarget::GFX9;
574 return getGeneration() < AMDGPUSubtarget::GFX9;
622 return getGeneration() > GFX9;
626 return getGeneration() >= GFX9;
632 return getGeneration() < GFX9;
821 return getGeneration() >= AMDGPUSubtarget::GFX9;
825 return getGeneration() >= AMDGPUSubtarget::GFX9;
[all...] |
| /external/mesa3d/src/amd/common/ |
| amd_family.h | 112 GFX9,
|
| ac_shader_util.c | 109 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
|
| ac_gpu_info.c | 252 info->chip_class = GFX9;
298 if (info->chip_class == GFX9) {
|
| /external/mesa3d/src/amd/vulkan/ |
| radv_image.c | 51 /* this causes hangs in some VK CTS tests on GFX9. */
121 (device->physical_device->rad_info.chip_class >= GFX9 &&
249 if (chip_class >= GFX9) {
251 va += image->surface.u.gfx9.stencil_offset;
253 va += image->surface.u.gfx9.surf_offset;
258 if (chip_class >= GFX9 ||
283 if (chip_class >= GFX9) {
288 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode);
289 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch);
291 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode)
[all...] |
| si_cmd_buffer.c | 421 if (physical_device->rad_info.chip_class >= GFX9) {
437 if (physical_device->rad_info.chip_class >= GFX9) {
506 if (physical_device->rad_info.chip_class >= GFX9) {
840 unsigned is_gfx8_mec = is_mec && chip_class < GFX9;
842 if (chip_class >= GFX9 || is_gfx8_mec) {
[all...] |
| radv_meta_bufimage.c | 32 /* GFX9 needs to use a 3D sampler to access 3D resources, so the shader has the options
135 if (device->physical_device->rad_info.chip_class >= GFX9)
211 if (device->physical_device->rad_info.chip_class >= GFX9) {
256 if (device->physical_device->rad_info.chip_class >= GFX9)
359 if (device->physical_device->rad_info.chip_class >= GFX9)
434 if (device->physical_device->rad_info.chip_class >= GFX9) {
573 if (device->physical_device->rad_info.chip_class >= GFX9)
648 if (device->physical_device->rad_info.chip_class >= GFX9) {
692 if (device->physical_device->rad_info.chip_class >= GFX9)
768 if (device->physical_device->rad_info.chip_class >= GFX9)
[all...] |
| radv_pipeline.c | 848 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_cp_dma.c | 48 unsigned max = sctx->b.chip_class >= GFX9 ?
71 if (sctx->b.chip_class >= GFX9)
80 if (sctx->b.chip_class >= GFX9)
90 if (sctx->b.chip_class >= GFX9 && !(flags & CP_DMA_CLEAR) &&
148 if ((sctx->b.chip_class >= GFX9 && coher == R600_COHERENCY_CB_META) ||
528 if (sctx->b.chip_class >= GFX9) {
|
| si_uvd.c | 115 enum ruvd_surface_type type = (sscreen->info.chip_class >= GFX9) ?
|
| si_pipe.c | 212 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
213 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
337 if (sctx->b.chip_class >= GFX9) {
526 /* gs_table_depth is not used by GFX9 */
527 if (sscreen->info.chip_class >= GFX9)
572 sscreen->info.chip_class = GFX9;
813 * on GFX9.
821 sscreen->info.chip_class >= GFX9) {
|
| si_state_draw.c | 119 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
120 if (sctx->b.chip_class >= GFX9) {
259 if (sctx->b.chip_class >= GFX9) {
443 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
446 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
447 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
597 if (sctx->b.chip_class >= GFX9)
622 if (sctx->b.chip_class >= GFX9)
702 if (sctx->b.chip_class >= GFX9) {
852 if (rctx->chip_class >= GFX9) {
[all...] |
| si_clear.c | 210 if (sctx->b.chip_class >= GFX9) {
248 assert(sscreen->info.chip_class >= GFX9 ||
252 if (sscreen->info.chip_class >= GFX9) {
254 assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
264 assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
268 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
269 rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
272 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
273 rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
276 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3
[all...] |
| si_state_binning.c | 345 assert(sctx->b.chip_class >= GFX9);
|
| si_descriptors.c | 327 if (sscreen->info.chip_class >= GFX9) {
330 va += tex->surface.u.gfx9.stencil_offset;
332 va += tex->surface.u.gfx9.surf_offset;
342 * GFX9 doesn't use (legacy) base_level_info.
344 if (sscreen->info.chip_class >= GFX9 ||
372 if (sscreen->info.chip_class >= GFX9) {
377 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
378 state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.stencil.epitch);
380 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode);
381 state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.surf.epitch)
[all...] |
| si_state.c | 112 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
129 sctx->b.chip_class == GFX9) &&
933 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
[all...] |
| cik_sdma.c | 57 radeon_emit(cs, ctx->b.chip_class >= GFX9 ? csize - 1 : csize);
104 radeon_emit(cs, sctx->b.chip_class >= GFX9 ? csize - 1 : csize);
|
| si_get.c | 243 /* TODO: GFX9 hangs. */
244 if (sscreen->info.chip_class >= GFX9)
731 /* Only 16 waves per thread-group on gfx9. */
732 if (screen->info.chip_class >= GFX9)
735 /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
|
| si_pipe.h | 870 if (sctx->b.chip_class >= GFX9) {
871 /* Single-sample color is coherent with shaders on GFX9, but
892 if (sctx->b.chip_class >= GFX9) {
894 * on GFX9, but L2 metadata must be flushed if shaders read
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| radeon_video.c | 151 if (rctx->chip_class < GFX9) {
168 if (rctx->chip_class < GFX9) {
178 surfaces[i]->u.gfx9.surf_offset += off;
179 for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j)
180 surfaces[i]->u.gfx9.offset[j] += off;
|
| r600_pipe_common.c | 62 if (ctx->chip_class >= GFX9) {
65 * prevent a GPU hang on GFX9.
70 if (ctx->chip_class == GFX9 &&
433 rctx->chip_class == GFX9) {
|
| r600_texture.c | 187 if (sscreen->info.chip_class >= GFX9) {
188 *stride = rtex->surface.u.gfx9.surf_pitch * rtex->surface.bpe;
189 *layer_stride = rtex->surface.u.gfx9.surf_slice_size;
196 return box->z * rtex->surface.u.gfx9.surf_slice_size +
197 rtex->surface.u.gfx9.offset[level] +
199 rtex->surface.u.gfx9.surf_pitch +
252 (sscreen->info.chip_class >= GFX9 ||
255 * GFX9 also supports Z16_UNORM.
303 if (sscreen->info.chip_class >= GFX9) {
305 surface->u.gfx9.surf_pitch = pitch
[all...] |
| radeon_vce.c | 225 if (sscreen->info.chip_class < GFX9) {
229 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256);
230 vpitch = align(enc->luma->u.gfx9.surf_height, 16);
462 cpb_size = (sscreen->info.chip_class < GFX9) ?
466 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
467 align(tmp_surf->u.gfx9.surf_height, 32);
|
| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_winsys.c | 48 /* LLVM 5.0 is required for GFX9. */
49 if (ws->info.chip_class >= GFX9 && HAVE_LLVM < 0x0500) {
|
| radv_amdgpu_bo.c | 54 if ((bo_flags & RADEON_FLAG_VA_UNCACHED) && ws->info.chip_class >= GFX9)
507 if (bo->ws->info.chip_class >= GFX9) {
508 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode);
|
