1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 */ 25 26 #include "ac_gpu_info.h" 27 #include "sid.h" 28 #include "gfx9d.h" 29 30 #include "util/u_math.h" 31 32 #include <stdio.h> 33 34 #include <xf86drm.h> 35 #include <amdgpu_drm.h> 36 37 #include <amdgpu.h> 38 39 #define CIK_TILE_MODE_COLOR_2D 14 40 41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f) 42 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0 43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4 44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5 45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6 46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7 47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8 48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9 49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10 50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11 51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12 52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13 53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14 54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16 55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17 56 57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info) 58 { 59 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D]; 60 61 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) { 62 case CIK__PIPE_CONFIG__ADDR_SURF_P2: 63 return 2; 64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16: 65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16: 66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32: 67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32: 68 return 4; 69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16: 70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16: 71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16: 72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16: 73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16: 74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32: 75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32: 76 return 8; 77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16: 78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16: 79 return 16; 80 default: 81 fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n"); 82 assert(!"this should never occur"); 83 return 2; 84 } 85 } 86 87 static bool has_syncobj(int fd) 88 { 89 uint64_t value; 90 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value)) 91 return false; 92 return value ? true : false; 93 } 94 95 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, 96 struct radeon_info *info, 97 struct amdgpu_gpu_info *amdinfo) 98 { 99 struct amdgpu_buffer_size_alignments alignment_info = {}; 100 struct amdgpu_heap_info vram, vram_vis, gtt; 101 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}; 102 struct drm_amdgpu_info_hw_ip vce = {}, vcn_dec = {}; 103 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {}; 104 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0; 105 int r, i, j; 106 drmDevicePtr devinfo; 107 108 /* Get PCI info. */ 109 r = drmGetDevice2(fd, 0, &devinfo); 110 if (r) { 111 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n"); 112 return false; 113 } 114 info->pci_domain = devinfo->businfo.pci->domain; 115 info->pci_bus = devinfo->businfo.pci->bus; 116 info->pci_dev = devinfo->businfo.pci->dev; 117 info->pci_func = devinfo->businfo.pci->func; 118 drmFreeDevice(&devinfo); 119 120 /* Query hardware and driver information. */ 121 r = amdgpu_query_gpu_info(dev, amdinfo); 122 if (r) { 123 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n"); 124 return false; 125 } 126 127 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info); 128 if (r) { 129 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n"); 130 return false; 131 } 132 133 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram); 134 if (r) { 135 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n"); 136 return false; 137 } 138 139 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 140 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 141 &vram_vis); 142 if (r) { 143 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n"); 144 return false; 145 } 146 147 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t); 148 if (r) { 149 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n"); 150 return false; 151 } 152 153 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma); 154 if (r) { 155 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n"); 156 return false; 157 } 158 159 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx); 160 if (r) { 161 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n"); 162 return false; 163 } 164 165 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute); 166 if (r) { 167 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n"); 168 return false; 169 } 170 171 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd); 172 if (r) { 173 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n"); 174 return false; 175 } 176 177 if (info->drm_major == 3 && info->drm_minor >= 17) { 178 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec); 179 if (r) { 180 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n"); 181 return false; 182 } 183 } 184 185 if (info->drm_major == 3 && info->drm_minor >= 17) { 186 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc); 187 if (r) { 188 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n"); 189 return false; 190 } 191 } 192 193 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0, 194 &info->me_fw_version, 195 &info->me_fw_feature); 196 if (r) { 197 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n"); 198 return false; 199 } 200 201 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0, 202 &info->pfp_fw_version, 203 &info->pfp_fw_feature); 204 if (r) { 205 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n"); 206 return false; 207 } 208 209 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0, 210 &info->ce_fw_version, 211 &info->ce_fw_feature); 212 if (r) { 213 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n"); 214 return false; 215 } 216 217 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0, 218 &uvd_version, &uvd_feature); 219 if (r) { 220 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n"); 221 return false; 222 } 223 224 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce); 225 if (r) { 226 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n"); 227 return false; 228 } 229 230 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0, 231 &vce_version, &vce_feature); 232 if (r) { 233 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n"); 234 return false; 235 } 236 237 /* Set chip identification. */ 238 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */ 239 info->vce_harvest_config = amdinfo->vce_harvest_config; 240 241 switch (info->pci_id) { 242 #define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break; 243 #include "pci_ids/radeonsi_pci_ids.h" 244 #undef CHIPSET 245 246 default: 247 fprintf(stderr, "amdgpu: Invalid PCI ID.\n"); 248 return false; 249 } 250 251 if (info->family >= CHIP_VEGA10) 252 info->chip_class = GFX9; 253 else if (info->family >= CHIP_TONGA) 254 info->chip_class = VI; 255 else if (info->family >= CHIP_BONAIRE) 256 info->chip_class = CIK; 257 else if (info->family >= CHIP_TAHITI) 258 info->chip_class = SI; 259 else { 260 fprintf(stderr, "amdgpu: Unknown family.\n"); 261 return false; 262 } 263 264 /* Set which chips have dedicated VRAM. */ 265 info->has_dedicated_vram = 266 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION); 267 268 /* Set hardware information. */ 269 info->gart_size = gtt.heap_size; 270 info->vram_size = vram.heap_size; 271 info->vram_vis_size = vram_vis.heap_size; 272 /* The kernel can split large buffers in VRAM but not in GTT, so large 273 * allocations can fail or cause buffer movement failures in the kernel. 274 */ 275 info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 0.7); 276 /* convert the shader clock from KHz to MHz */ 277 info->max_shader_clock = amdinfo->max_engine_clk / 1000; 278 info->max_se = amdinfo->num_shader_engines; 279 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine; 280 info->has_hw_decode = 281 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0); 282 info->uvd_fw_version = 283 uvd.available_rings ? uvd_version : 0; 284 info->vce_fw_version = 285 vce.available_rings ? vce_version : 0; 286 info->has_userptr = true; 287 info->has_syncobj = has_syncobj(fd); 288 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20; 289 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21; 290 info->has_ctx_priority = info->drm_minor >= 22; 291 info->num_render_backends = amdinfo->rb_pipes; 292 info->clock_crystal_freq = amdinfo->gpu_counter_freq; 293 if (!info->clock_crystal_freq) { 294 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n"); 295 info->clock_crystal_freq = 1; 296 } 297 info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */ 298 if (info->chip_class == GFX9) { 299 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg); 300 info->pipe_interleave_bytes = 301 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg); 302 } else { 303 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo); 304 info->pipe_interleave_bytes = 305 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg); 306 } 307 info->has_virtual_memory = true; 308 309 assert(util_is_power_of_two(dma.available_rings + 1)); 310 assert(util_is_power_of_two(compute.available_rings + 1)); 311 312 info->num_sdma_rings = util_bitcount(dma.available_rings); 313 info->num_compute_rings = util_bitcount(compute.available_rings); 314 315 /* Get the number of good compute units. */ 316 info->num_good_compute_units = 0; 317 for (i = 0; i < info->max_se; i++) 318 for (j = 0; j < info->max_sh_per_se; j++) 319 info->num_good_compute_units += 320 util_bitcount(amdinfo->cu_bitmap[i][j]); 321 322 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode, 323 sizeof(amdinfo->gb_tile_mode)); 324 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask; 325 326 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode, 327 sizeof(amdinfo->gb_macro_tile_mode)); 328 329 info->pte_fragment_size = alignment_info.size_local; 330 info->gart_page_size = alignment_info.size_remote; 331 332 if (info->chip_class == SI) 333 info->gfx_ib_pad_with_type2 = TRUE; 334 335 unsigned ib_align = 0; 336 ib_align = MAX2(ib_align, gfx.ib_start_alignment); 337 ib_align = MAX2(ib_align, compute.ib_start_alignment); 338 ib_align = MAX2(ib_align, dma.ib_start_alignment); 339 ib_align = MAX2(ib_align, uvd.ib_start_alignment); 340 ib_align = MAX2(ib_align, vce.ib_start_alignment); 341 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment); 342 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment); 343 info->ib_start_alignment = ib_align; 344 345 return true; 346 } 347 348 void ac_compute_driver_uuid(char *uuid, size_t size) 349 { 350 char amd_uuid[] = "AMD-MESA-DRV"; 351 352 assert(size >= sizeof(amd_uuid)); 353 354 memset(uuid, 0, size); 355 strncpy(uuid, amd_uuid, size); 356 } 357 358 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size) 359 { 360 uint32_t *uint_uuid = (uint32_t*)uuid; 361 362 assert(size >= sizeof(uint32_t)*4); 363 364 /** 365 * Use the device info directly instead of using a sha1. GL/VK UUIDs 366 * are 16 byte vs 20 byte for sha1, and the truncation that would be 367 * required would get rid of part of the little entropy we have. 368 * */ 369 memset(uuid, 0, size); 370 uint_uuid[0] = info->pci_domain; 371 uint_uuid[1] = info->pci_bus; 372 uint_uuid[2] = info->pci_dev; 373 uint_uuid[3] = info->pci_func; 374 } 375 376 void ac_print_gpu_info(struct radeon_info *info) 377 { 378 printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n", 379 info->pci_domain, info->pci_bus, 380 info->pci_dev, info->pci_func); 381 printf("pci_id = 0x%x\n", info->pci_id); 382 printf("family = %i\n", info->family); 383 printf("chip_class = %i\n", info->chip_class); 384 printf("pte_fragment_size = %u\n", info->pte_fragment_size); 385 printf("gart_page_size = %u\n", info->gart_page_size); 386 printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024)); 387 printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024)); 388 printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024)); 389 printf("max_alloc_size = %i MB\n", 390 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024)); 391 printf("min_alloc_size = %u\n", info->min_alloc_size); 392 printf("has_dedicated_vram = %u\n", info->has_dedicated_vram); 393 printf("has_virtual_memory = %i\n", info->has_virtual_memory); 394 printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2); 395 printf("has_hw_decode = %u\n", info->has_hw_decode); 396 printf("num_sdma_rings = %i\n", info->num_sdma_rings); 397 printf("num_compute_rings = %u\n", info->num_compute_rings); 398 printf("uvd_fw_version = %u\n", info->uvd_fw_version); 399 printf("vce_fw_version = %u\n", info->vce_fw_version); 400 printf("me_fw_version = %i\n", info->me_fw_version); 401 printf("me_fw_feature = %i\n", info->me_fw_feature); 402 printf("pfp_fw_version = %i\n", info->pfp_fw_version); 403 printf("pfp_fw_feature = %i\n", info->pfp_fw_feature); 404 printf("ce_fw_version = %i\n", info->ce_fw_version); 405 printf("ce_fw_feature = %i\n", info->ce_fw_feature); 406 printf("vce_harvest_config = %i\n", info->vce_harvest_config); 407 printf("clock_crystal_freq = %i\n", info->clock_crystal_freq); 408 printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size); 409 printf("drm = %i.%i.%i\n", info->drm_major, 410 info->drm_minor, info->drm_patchlevel); 411 printf("has_userptr = %i\n", info->has_userptr); 412 printf("has_syncobj = %u\n", info->has_syncobj); 413 printf("has_fence_to_handle = %u\n", info->has_fence_to_handle); 414 415 printf("r600_max_quad_pipes = %i\n", info->r600_max_quad_pipes); 416 printf("max_shader_clock = %i\n", info->max_shader_clock); 417 printf("num_good_compute_units = %i\n", info->num_good_compute_units); 418 printf("max_se = %i\n", info->max_se); 419 printf("max_sh_per_se = %i\n", info->max_sh_per_se); 420 421 printf("r600_gb_backend_map = %i\n", info->r600_gb_backend_map); 422 printf("r600_gb_backend_map_valid = %i\n", info->r600_gb_backend_map_valid); 423 printf("r600_num_banks = %i\n", info->r600_num_banks); 424 printf("num_render_backends = %i\n", info->num_render_backends); 425 printf("num_tile_pipes = %i\n", info->num_tile_pipes); 426 printf("pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes); 427 printf("enabled_rb_mask = 0x%x\n", info->enabled_rb_mask); 428 printf("max_alignment = %u\n", (unsigned)info->max_alignment); 429 } 430
