1 /* 2 * Copyright (c) 2015 Hisilicon Limited. 3 * 4 * Author: Bintian Wang <bintian.wang (at) huawei.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __DT_BINDINGS_CLOCK_HI6220_H 12 #define __DT_BINDINGS_CLOCK_HI6220_H 13 14 /* clk in Hi6220 AO (always on) controller */ 15 #define HI6220_NONE_CLOCK 0 16 17 /* fixed rate clocks */ 18 #define HI6220_REF32K 1 19 #define HI6220_CLK_TCXO 2 20 #define HI6220_MMC1_PAD 3 21 #define HI6220_MMC2_PAD 4 22 #define HI6220_MMC0_PAD 5 23 #define HI6220_PLL_BBP 6 24 #define HI6220_PLL_GPU 7 25 #define HI6220_PLL1_DDR 8 26 #define HI6220_PLL_SYS 9 27 #define HI6220_PLL_SYS_MEDIA 10 28 #define HI6220_DDR_SRC 11 29 #define HI6220_PLL_MEDIA 12 30 #define HI6220_PLL_DDR 13 31 32 /* fixed factor clocks */ 33 #define HI6220_300M 14 34 #define HI6220_150M 15 35 #define HI6220_PICOPHY_SRC 16 36 #define HI6220_MMC0_SRC_SEL 17 37 #define HI6220_MMC1_SRC_SEL 18 38 #define HI6220_MMC2_SRC_SEL 19 39 #define HI6220_VPU_CODEC 20 40 #define HI6220_MMC0_SMP 21 41 #define HI6220_MMC1_SMP 22 42 #define HI6220_MMC2_SMP 23 43 44 /* gate clocks */ 45 #define HI6220_WDT0_PCLK 24 46 #define HI6220_WDT1_PCLK 25 47 #define HI6220_WDT2_PCLK 26 48 #define HI6220_TIMER0_PCLK 27 49 #define HI6220_TIMER1_PCLK 28 50 #define HI6220_TIMER2_PCLK 29 51 #define HI6220_TIMER3_PCLK 30 52 #define HI6220_TIMER4_PCLK 31 53 #define HI6220_TIMER5_PCLK 32 54 #define HI6220_TIMER6_PCLK 33 55 #define HI6220_TIMER7_PCLK 34 56 #define HI6220_TIMER8_PCLK 35 57 #define HI6220_UART0_PCLK 36 58 59 #define HI6220_AO_NR_CLKS 37 60 61 /* clk in Hi6220 systrl */ 62 /* gate clock */ 63 #define HI6220_MMC0_CLK 1 64 #define HI6220_MMC0_CIUCLK 2 65 #define HI6220_MMC1_CLK 3 66 #define HI6220_MMC1_CIUCLK 4 67 #define HI6220_MMC2_CLK 5 68 #define HI6220_MMC2_CIUCLK 6 69 #define HI6220_USBOTG_HCLK 7 70 #define HI6220_CLK_PICOPHY 8 71 #define HI6220_HIFI 9 72 #define HI6220_DACODEC_PCLK 10 73 #define HI6220_EDMAC_ACLK 11 74 #define HI6220_CS_ATB 12 75 #define HI6220_I2C0_CLK 13 76 #define HI6220_I2C1_CLK 14 77 #define HI6220_I2C2_CLK 15 78 #define HI6220_I2C3_CLK 16 79 #define HI6220_UART1_PCLK 17 80 #define HI6220_UART2_PCLK 18 81 #define HI6220_UART3_PCLK 19 82 #define HI6220_UART4_PCLK 20 83 #define HI6220_SPI_CLK 21 84 #define HI6220_TSENSOR_CLK 22 85 #define HI6220_MMU_CLK 23 86 #define HI6220_HIFI_SEL 24 87 #define HI6220_MMC0_SYSPLL 25 88 #define HI6220_MMC1_SYSPLL 26 89 #define HI6220_MMC2_SYSPLL 27 90 #define HI6220_MMC0_SEL 28 91 #define HI6220_MMC1_SEL 29 92 #define HI6220_BBPPLL_SEL 30 93 #define HI6220_MEDIA_PLL_SRC 31 94 #define HI6220_MMC2_SEL 32 95 #define HI6220_CS_ATB_SYSPLL 33 96 97 /* mux clocks */ 98 #define HI6220_MMC0_SRC 34 99 #define HI6220_MMC0_SMP_IN 35 100 #define HI6220_MMC1_SRC 36 101 #define HI6220_MMC1_SMP_IN 37 102 #define HI6220_MMC2_SRC 38 103 #define HI6220_MMC2_SMP_IN 39 104 #define HI6220_HIFI_SRC 40 105 #define HI6220_UART1_SRC 41 106 #define HI6220_UART2_SRC 42 107 #define HI6220_UART3_SRC 43 108 #define HI6220_UART4_SRC 44 109 #define HI6220_MMC0_MUX0 45 110 #define HI6220_MMC1_MUX0 46 111 #define HI6220_MMC2_MUX0 47 112 #define HI6220_MMC0_MUX1 48 113 #define HI6220_MMC1_MUX1 49 114 #define HI6220_MMC2_MUX1 50 115 116 /* divider clocks */ 117 #define HI6220_CLK_BUS 51 118 #define HI6220_MMC0_DIV 52 119 #define HI6220_MMC1_DIV 53 120 #define HI6220_MMC2_DIV 54 121 #define HI6220_HIFI_DIV 55 122 #define HI6220_BBPPLL0_DIV 56 123 #define HI6220_CS_DAPB 57 124 #define HI6220_CS_ATB_DIV 58 125 126 #define HI6220_SYS_NR_CLKS 59 127 128 /* clk in Hi6220 media controller */ 129 /* gate clocks */ 130 #define HI6220_DSI_PCLK 1 131 #define HI6220_G3D_PCLK 2 132 #define HI6220_ACLK_CODEC_VPU 3 133 #define HI6220_ISP_SCLK 4 134 #define HI6220_ADE_CORE 5 135 #define HI6220_MED_MMU 6 136 #define HI6220_CFG_CSI4PHY 7 137 #define HI6220_CFG_CSI2PHY 8 138 #define HI6220_ISP_SCLK_GATE 9 139 #define HI6220_ISP_SCLK_GATE1 10 140 #define HI6220_ADE_CORE_GATE 11 141 #define HI6220_CODEC_VPU_GATE 12 142 #define HI6220_MED_SYSPLL 13 143 144 /* mux clocks */ 145 #define HI6220_1440_1200 14 146 #define HI6220_1000_1200 15 147 #define HI6220_1000_1440 16 148 149 /* divider clocks */ 150 #define HI6220_CODEC_JPEG 17 151 #define HI6220_ISP_SCLK_SRC 18 152 #define HI6220_ISP_SCLK1 19 153 #define HI6220_ADE_CORE_SRC 20 154 #define HI6220_ADE_PIX_SRC 21 155 #define HI6220_G3D_CLK 22 156 #define HI6220_CODEC_VPU_SRC 23 157 158 #define HI6220_MEDIA_NR_CLKS 24 159 160 /* clk in Hi6220 power controller */ 161 /* gate clocks */ 162 #define HI6220_PLL_GPU_GATE 1 163 #define HI6220_PLL1_DDR_GATE 2 164 #define HI6220_PLL_DDR_GATE 3 165 #define HI6220_PLL_MEDIA_GATE 4 166 #define HI6220_PLL0_BBP_GATE 5 167 168 /* divider clocks */ 169 #define HI6220_DDRC_SRC 6 170 #define HI6220_DDRC_AXI1 7 171 172 #define HI6220_POWER_NR_CLKS 8 173 #endif 174
