| /external/llvm/lib/Target/AArch64/ |
| AArch64Subtarget.h | 54 bool HasV8_1aOps = false;
165 bool hasV8_1aOps() const { return HasV8_1aOps; }
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64Subtarget.h | 66 bool HasV8_1aOps = false;
210 bool hasV8_1aOps() const { return HasV8_1aOps; }
|
| /external/llvm/lib/Target/ARM/ |
| ARMSubtarget.h | 96 bool HasV8_1aOps = false;
402 bool hasV8_1aOps() const { return HasV8_1aOps; }
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMSubtarget.h | 152 bool HasV8_1aOps = false;
528 bool hasV8_1aOps() const { return HasV8_1aOps; }
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMTargetStreamer.cpp | 222 STI.hasFeature(ARM::HasV8_1aOps)
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| AArch64GenSubtargetInfo.inc | 60 HasV8_1aOps = 44,
149 { "thunderx2t99", "Cavium ThunderX2 processors", { AArch64::ProcThunderX2T99 }, { AArch64::FeatureAggressiveFMA, AArch64::FeatureCRC, AArch64::FeatureCrypto, AArch64::FeatureFPARMv8, AArch64::FeatureArithmeticBccFusion, AArch64::FeatureNEON, AArch64::FeaturePostRAScheduler, AArch64::FeaturePredictableSelectIsExpensive, AArch64::FeatureLSE, AArch64::HasV8_1aOps } },
156 { "v8.1a", "Support ARM v8.1a instructions", { AArch64::HasV8_1aOps }, { AArch64::FeatureCRC, AArch64::FeatureLSE, AArch64::FeatureRDM } },
157 { "v8.2a", "Support ARM v8.2a instructions", { AArch64::HasV8_2aOps }, { AArch64::HasV8_1aOps, AArch64::FeatureRAS } },
[all...] |
| AArch64GenMCCodeEmitter.inc | [all...] |
| AArch64GenAsmMatcher.inc | [all...] |
| AArch64GenDisassemblerTables.inc | [all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| ARMGenSubtargetInfo.inc | 130 HasV8_1aOps = 114,
223 { "armv8.1-a", "ARMv81a architecture", { ARM::ARMv81a }, { ARM::HasV8_1aOps, ARM::FeatureAClass, ARM::FeatureDB, ARM::FeatureFPARMv8, ARM::FeatureNEON, ARM::FeatureDSP, ARM::FeatureTrustZone, ARM::FeatureMP, ARM::FeatureVirtualization, ARM::FeatureCrypto, ARM::FeatureCRC } },
308 { "v8.1a", "Support ARM v8.1a instructions", { ARM::HasV8_1aOps }, { ARM::HasV8Ops } },
309 { "v8.2a", "Support ARM v8.2a instructions", { ARM::HasV8_2aOps }, { ARM::HasV8_1aOps } },
[all...] |
| ARMGenDisassemblerTables.inc | [all...] |
| ARMGenMCCodeEmitter.inc | [all...] |
| ARMGenAsmMatcher.inc | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 296 bool hasV8_1aOps() const {
297 return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 497 bool hasV8_1aOps() const {
498 return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
[all...] |
