| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonDepTimingClasses.h | 23 case Hexagon::Sched::tc_16d0d8d5:
24 case Hexagon::Sched::tc_1853ea6d:
25 case Hexagon::Sched::tc_60571023:
26 case Hexagon::Sched::tc_7934b9df:
27 case Hexagon::Sched::tc_8fd5f294:
28 case Hexagon::Sched::tc_b9c0b731:
29 case Hexagon::Sched::tc_bcc96cee:
30 case Hexagon::Sched::tc_c6ce9b3f:
31 case Hexagon::Sched::tc_c6ebf8dd:
32 case Hexagon::Sched::tc_c82dc1ff
[all...] |
| HexagonRegisterInfo.cpp | 1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
16 #include "Hexagon.h"
46 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
51 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
52 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1
[all...] |
| HexagonInstrInfo.cpp | 1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
15 #include "Hexagon.h"
65 #define DEBUG_TYPE "hexagon-instrinfo"
73 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
77 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
80 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
103 /// Constants for Hexagon instructions.
119 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP)
[all...] |
| HexagonAsmPrinter.cpp | 1 //===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
11 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
17 #include "Hexagon.h"
68 assert(Hexagon::IntRegsRegClass.contains(Reg));
71 assert(Hexagon::DoubleRegsRegClass.contains(Pair));
130 // Hexagon never has a prefix.
142 if (Hexagon::DoubleRegsRegClass.contains(RegNumber))
144 Hexagon::isub_lo :
145 Hexagon::isub_hi);
279 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8
[all...] |
| HexagonDepArch.h | 17 namespace Hexagon {
19 } // namespace Hexagon
|
| HexagonNewValueJump.cpp | 1 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
10 // This implements NewValueJump pass in Hexagon.
24 #include "Hexagon.h"
55 #define DEBUG_TYPE "hexagon-nvj"
86 StringRef getPassName() const override { return "Hexagon NewValueJump"; }
109 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
110 "Hexagon NewValueJump", false, false)
112 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
113 "Hexagon NewValueJump", false, false)
157 if (!Hexagon::IntRegsRegClass.contains(Op.getReg())
[all...] |
| HexagonCFGOptimizer.cpp | 10 #include "Hexagon.h"
49 StringRef getPassName() const override { return "Hexagon CFG Optimizer"; }
64 case Hexagon::J2_jumpt:
65 case Hexagon::J2_jumptpt:
66 case Hexagon::J2_jumpf:
67 case Hexagon::J2_jumpfpt:
68 case Hexagon::J2_jumptnew:
69 case Hexagon::J2_jumpfnew:
70 case Hexagon::J2_jumptnewpt:
71 case Hexagon::J2_jumpfnewpt
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
16 #include "Hexagon.h"
42 : HexagonGenRegisterInfo(Hexagon::R31) {}
46 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
47 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1
[all...] |
| HexagonInstrInfo.cpp | 1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
15 #include "Hexagon.h"
35 #define DEBUG_TYPE "hexagon-instrinfo"
44 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
48 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
51 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
71 /// Constants for Hexagon instructions.
104 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP)
[all...] |
| HexagonNewValueJump.cpp | 1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
10 // This implements NewValueJump pass in Hexagon.
24 #include "Hexagon.h"
47 #define DEBUG_TYPE "hexagon-nvj"
83 return "Hexagon NewValueJump";
103 INITIALIZE_PASS_BEGIN(HexagonNewValueJump, "hexagon-nvj",
104 "Hexagon NewValueJump", false, false)
106 INITIALIZE_PASS_END(HexagonNewValueJump, "hexagon-nvj",
107 "Hexagon NewValueJump", false, false)
183 if (MII->getOpcode() == Hexagon::J2_call
[all...] |
| HexagonAsmPrinter.cpp | 1 //===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly --===//
11 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
16 #include "Hexagon.h"
66 "hexagon-align-calls", cl::Hidden, cl::init(true),
67 cl::desc("Insert falign after call instruction for Hexagon target"));
72 assert(Hexagon::IntRegsRegClass.contains(Reg));
75 assert(Hexagon::DoubleRegsRegClass.contains(Pair));
141 // Hexagon never has a prefix.
264 case Hexagon::A2_iconst: {
265 Inst.setOpcode(Hexagon::A2_addi)
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 24 using namespace Hexagon;
26 #define DEBUG_TYPE "hexagon-mcduplex-info"
188 case Hexagon::L2_loadri_io:
195 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
205 case Hexagon::L2_loadrub_io:
225 case Hexagon::L2_loadrh_io:
226 case Hexagon::L2_loadruh_io:
236 case Hexagon::L2_loadrb_io:
246 case Hexagon::L2_loadrd_io:
251 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &
[all...] |
| HexagonMCCodeEmitter.cpp | 1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
10 #include "Hexagon.h"
31 using namespace Hexagon;
98 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
99 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
100 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
114 static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10
[all...] |
| HexagonMCCompound.cpp | 2 //=== HexagonMCCompound.cpp - Hexagon Compound checker -------===//
14 #include "Hexagon.h"
28 using namespace Hexagon;
30 #define DEBUG_TYPE "hexagon-mccompound"
95 case Hexagon::C2_cmpeq:
96 case Hexagon::C2_cmpgt:
97 case Hexagon::C2_cmpgtu:
103 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
108 case Hexagon::C2_cmpeqi
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
10 #define DEBUG_TYPE "hexagon-disassembler"
12 #include "Hexagon.h"
37 using namespace Hexagon;
43 /// Hexagon disassembler for all Hexagon platforms.
228 MI.setOpcode(Hexagon::BUNDLE);
255 case Hexagon::S2_allocframe:
256 if (MI.getOperand(0).getReg() == Hexagon::R29) {
257 MI.setOpcode(Hexagon::S6_allocframe_to_raw)
[all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
10 #define DEBUG_TYPE "hexagon-disassembler"
12 #include "Hexagon.h"
35 using namespace Hexagon;
40 /// \brief Hexagon disassembler for all Hexagon platforms.
283 MI.setOpcode(Hexagon::DuplexIClass0);
304 // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
322 MI.getOpcode() == Hexagon::A4_ext) {
336 unsigned reg = i->getReg() - Hexagon::R0
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 32 using namespace Hexagon;
34 #define DEBUG_TYPE "hexagon-mcduplex-info"
196 case Hexagon::L2_loadri_io:
203 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
213 case Hexagon::L2_loadrub_io:
233 case Hexagon::L2_loadrh_io:
234 case Hexagon::L2_loadruh_io:
244 case Hexagon::L2_loadrb_io:
254 case Hexagon::L2_loadrd_io:
259 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &
[all...] |
| HexagonMCCompound.cpp | 1 //=== HexagonMCCompound.cpp - Hexagon Compound checker -------------------===//
14 #include "Hexagon.h"
27 using namespace Hexagon;
29 #define DEBUG_TYPE "hexagon-mccompound"
93 case Hexagon::C2_cmpeq:
94 case Hexagon::C2_cmpgt:
95 case Hexagon::C2_cmpgtu:
101 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
106 case Hexagon::C2_cmpeqi
[all...] |
| /external/llvm/test/MC/Hexagon/instructions/ |
| memop.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
2 # Hexagon Programmer's Reference Manual 11.6 MEMOP
|
| nv_j.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
2 # Hexagon Programmer's Reference Manual 11.7.1 NV/J
|
| alu32_alu.s | 1 # RUN: llvm-mc -triple hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
2 # Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU
|
| alu32_perm.s | 1 # RUN: llvm-mc -triple hexagon -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s
2 # Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM
|
| alu32_pred.s | 1 # RUN: llvm-mc -triple hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
2 # Hexagon Programmer's Reference Manual 11.1.3 ALU32/PRED
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/instructions/ |
| memop.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
2 # Hexagon Programmer's Reference Manual 11.6 MEMOP
|
| nv_j.s | 1 # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
2 # Hexagon Programmer's Reference Manual 11.7.1 NV/J
|
