Home | History | Annotate | Download | only in Hexagon 
      1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Hexagon implementation of the TargetRegisterInfo
     11 // class.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #include "HexagonRegisterInfo.h"
     16 #include "Hexagon.h"
     17 #include "HexagonMachineFunctionInfo.h"
     18 #include "HexagonSubtarget.h"
     19 #include "HexagonTargetMachine.h"
     20 #include "llvm/ADT/BitVector.h"
     21 #include "llvm/ADT/STLExtras.h"
     22 #include "llvm/CodeGen/LiveIntervals.h"
     23 #include "llvm/CodeGen/MachineFrameInfo.h"
     24 #include "llvm/CodeGen/MachineFunction.h"
     25 #include "llvm/CodeGen/MachineFunctionPass.h"
     26 #include "llvm/CodeGen/MachineInstrBuilder.h"
     27 #include "llvm/CodeGen/MachineRegisterInfo.h"
     28 #include "llvm/CodeGen/PseudoSourceValue.h"
     29 #include "llvm/CodeGen/RegisterScavenging.h"
     30 #include "llvm/CodeGen/TargetInstrInfo.h"
     31 #include "llvm/IR/Function.h"
     32 #include "llvm/IR/Type.h"
     33 #include "llvm/MC/MachineLocation.h"
     34 #include "llvm/Support/Debug.h"
     35 #include "llvm/Support/ErrorHandling.h"
     36 #include "llvm/Support/raw_ostream.h"
     37 #include "llvm/Target/TargetMachine.h"
     38 #include "llvm/Target/TargetOptions.h"
     39 
     40 #define GET_REGINFO_TARGET_DESC
     41 #include "HexagonGenRegisterInfo.inc"
     42 
     43 using namespace llvm;
     44 
     45 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode)
     46     : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
     47                              0/*PC*/, HwMode) {}
     48 
     49 
     50 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const {
     51   return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
     52          R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
     53 }
     54 
     55 const MCPhysReg *
     56 HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF,
     57       const TargetRegisterClass *RC) const {
     58   using namespace Hexagon;
     59 
     60   static const MCPhysReg Int32[] = {
     61     R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
     62   };
     63   static const MCPhysReg Int64[] = {
     64     D0, D1, D2, D3, D4, D5, D6, D7, 0
     65   };
     66   static const MCPhysReg Pred[] = {
     67     P0, P1, P2, P3, 0
     68   };
     69   static const MCPhysReg VecSgl[] = {
     70      V0,  V1,  V2,  V3,  V4,  V5,  V6,  V7,  V8,  V9, V10, V11, V12, V13,
     71     V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
     72     V28, V29, V30, V31,   0
     73   };
     74   static const MCPhysReg VecDbl[] = {
     75     W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
     76   };
     77 
     78   switch (RC->getID()) {
     79     case IntRegsRegClassID:
     80       return Int32;
     81     case DoubleRegsRegClassID:
     82       return Int64;
     83     case PredRegsRegClassID:
     84       return Pred;
     85     case HvxVRRegClassID:
     86       return VecSgl;
     87     case HvxWRRegClassID:
     88       return VecDbl;
     89     default:
     90       break;
     91   }
     92 
     93   static const MCPhysReg Empty[] = { 0 };
     94 #ifndef NDEBUG
     95   dbgs() << "Register class: " << getRegClassName(RC) << "\n";
     96 #endif
     97   llvm_unreachable("Unexpected register class");
     98   return Empty;
     99 }
    100 
    101 
    102 const MCPhysReg *
    103 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
    104   static const MCPhysReg CalleeSavedRegsV3[] = {
    105     Hexagon::R16,   Hexagon::R17,   Hexagon::R18,   Hexagon::R19,
    106     Hexagon::R20,   Hexagon::R21,   Hexagon::R22,   Hexagon::R23,
    107     Hexagon::R24,   Hexagon::R25,   Hexagon::R26,   Hexagon::R27, 0
    108   };
    109 
    110   // Functions that contain a call to __builtin_eh_return also save the first 4
    111   // parameter registers.
    112   static const MCPhysReg CalleeSavedRegsV3EHReturn[] = {
    113     Hexagon::R0,    Hexagon::R1,    Hexagon::R2,    Hexagon::R3,
    114     Hexagon::R16,   Hexagon::R17,   Hexagon::R18,   Hexagon::R19,
    115     Hexagon::R20,   Hexagon::R21,   Hexagon::R22,   Hexagon::R23,
    116     Hexagon::R24,   Hexagon::R25,   Hexagon::R26,   Hexagon::R27, 0
    117   };
    118 
    119   bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn();
    120 
    121   switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
    122   case Hexagon::ArchEnum::V4:
    123   case Hexagon::ArchEnum::V5:
    124   case Hexagon::ArchEnum::V55:
    125   case Hexagon::ArchEnum::V60:
    126   case Hexagon::ArchEnum::V62:
    127   case Hexagon::ArchEnum::V65:
    128     return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3;
    129   }
    130 
    131   llvm_unreachable("Callee saved registers requested for unknown architecture "
    132                    "version");
    133 }
    134 
    135 
    136 const uint32_t *HexagonRegisterInfo::getCallPreservedMask(
    137       const MachineFunction &MF, CallingConv::ID) const {
    138   return HexagonCSR_RegMask;
    139 }
    140 
    141 
    142 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
    143   const {
    144   BitVector Reserved(getNumRegs());
    145   Reserved.set(Hexagon::R29);
    146   Reserved.set(Hexagon::R30);
    147   Reserved.set(Hexagon::R31);
    148   Reserved.set(Hexagon::VTMP);
    149 
    150   // Guest registers.
    151   Reserved.set(Hexagon::GELR);        // G0
    152   Reserved.set(Hexagon::GSR);         // G1
    153   Reserved.set(Hexagon::GOSP);        // G2
    154   Reserved.set(Hexagon::G3);          // G3
    155 
    156   // Control registers.
    157   Reserved.set(Hexagon::SA0);         // C0
    158   Reserved.set(Hexagon::LC0);         // C1
    159   Reserved.set(Hexagon::SA1);         // C2
    160   Reserved.set(Hexagon::LC1);         // C3
    161   Reserved.set(Hexagon::P3_0);        // C4
    162   Reserved.set(Hexagon::USR);         // C8
    163   Reserved.set(Hexagon::PC);          // C9
    164   Reserved.set(Hexagon::UGP);         // C10
    165   Reserved.set(Hexagon::GP);          // C11
    166   Reserved.set(Hexagon::CS0);         // C12
    167   Reserved.set(Hexagon::CS1);         // C13
    168   Reserved.set(Hexagon::UPCYCLELO);   // C14
    169   Reserved.set(Hexagon::UPCYCLEHI);   // C15
    170   Reserved.set(Hexagon::FRAMELIMIT);  // C16
    171   Reserved.set(Hexagon::FRAMEKEY);    // C17
    172   Reserved.set(Hexagon::PKTCOUNTLO);  // C18
    173   Reserved.set(Hexagon::PKTCOUNTHI);  // C19
    174   Reserved.set(Hexagon::UTIMERLO);    // C30
    175   Reserved.set(Hexagon::UTIMERHI);    // C31
    176   // Out of the control registers, only C8 is explicitly defined in
    177   // HexagonRegisterInfo.td. If others are defined, make sure to add
    178   // them here as well.
    179   Reserved.set(Hexagon::C8);
    180   Reserved.set(Hexagon::USR_OVF);
    181 
    182   if (MF.getSubtarget<HexagonSubtarget>().hasReservedR19())
    183     Reserved.set(Hexagon::R19);
    184 
    185   for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x))
    186     markSuperRegs(Reserved, x);
    187 
    188   return Reserved;
    189 }
    190 
    191 
    192 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
    193                                               int SPAdj, unsigned FIOp,
    194                                               RegScavenger *RS) const {
    195   //
    196   // Hexagon_TODO: Do we need to enforce this for Hexagon?
    197   assert(SPAdj == 0 && "Unexpected");
    198 
    199   MachineInstr &MI = *II;
    200   MachineBasicBlock &MB = *MI.getParent();
    201   MachineFunction &MF = *MB.getParent();
    202   auto &HST = MF.getSubtarget<HexagonSubtarget>();
    203   auto &HII = *HST.getInstrInfo();
    204   auto &HFI = *HST.getFrameLowering();
    205 
    206   unsigned BP = 0;
    207   int FI = MI.getOperand(FIOp).getIndex();
    208   // Select the base pointer (BP) and calculate the actual offset from BP
    209   // to the beginning of the object at index FI.
    210   int Offset = HFI.getFrameIndexReference(MF, FI, BP);
    211   // Add the offset from the instruction.
    212   int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
    213   bool IsKill = false;
    214 
    215   unsigned Opc = MI.getOpcode();
    216   switch (Opc) {
    217     case Hexagon::PS_fia:
    218       MI.setDesc(HII.get(Hexagon::A2_addi));
    219       MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
    220       MI.RemoveOperand(FIOp+1);
    221       return;
    222     case Hexagon::PS_fi:
    223       // Set up the instruction for updating below.
    224       MI.setDesc(HII.get(Hexagon::A2_addi));
    225       break;
    226   }
    227 
    228   if (!HII.isValidOffset(Opc, RealOffset, this)) {
    229     // If the offset is not valid, calculate the address in a temporary
    230     // register and use it with offset 0.
    231     auto &MRI = MF.getRegInfo();
    232     unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
    233     const DebugLoc &DL = MI.getDebugLoc();
    234     BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
    235       .addReg(BP)
    236       .addImm(RealOffset);
    237     BP = TmpR;
    238     RealOffset = 0;
    239     IsKill = true;
    240   }
    241 
    242   MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
    243   MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
    244 }
    245 
    246 
    247 bool HexagonRegisterInfo::shouldCoalesce(MachineInstr *MI,
    248       const TargetRegisterClass *SrcRC, unsigned SubReg,
    249       const TargetRegisterClass *DstRC, unsigned DstSubReg,
    250       const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
    251   // Coalescing will extend the live interval of the destination register.
    252   // If the destination register is a vector pair, avoid introducing function
    253   // calls into the interval, since it could result in a spilling of a pair
    254   // instead of a single vector.
    255   MachineFunction &MF = *MI->getParent()->getParent();
    256   const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
    257   if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())
    258     return true;
    259   bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
    260   bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
    261   if (!SmallSrc && !SmallDst)
    262     return true;
    263 
    264   unsigned DstReg = MI->getOperand(0).getReg();
    265   unsigned SrcReg = MI->getOperand(1).getReg();
    266   const SlotIndexes &Indexes = *LIS.getSlotIndexes();
    267   auto HasCall = [&Indexes] (const LiveInterval::Segment &S) {
    268     for (SlotIndex I = S.start.getBaseIndex(), E = S.end.getBaseIndex();
    269          I != E; I = I.getNextIndex()) {
    270       if (const MachineInstr *MI = Indexes.getInstructionFromIndex(I))
    271         if (MI->isCall())
    272           return true;
    273     }
    274     return false;
    275   };
    276 
    277   if (SmallSrc == SmallDst) {
    278     // Both must be true, because the case for both being false was
    279     // checked earlier. Both registers will be coalesced into a register
    280     // of a wider class (HvxWR), and we don't want its live range to
    281     // span over calls.
    282     return !any_of(LIS.getInterval(DstReg), HasCall) &&
    283            !any_of(LIS.getInterval(SrcReg), HasCall);
    284   }
    285 
    286   // If one register is large (HvxWR) and the other is small (HvxVR), then
    287   // coalescing is ok if the large is already live across a function call,
    288   // or if the small one is not.
    289   unsigned SmallReg = SmallSrc ? SrcReg : DstReg;
    290   unsigned LargeReg = SmallSrc ? DstReg : SrcReg;
    291   return  any_of(LIS.getInterval(LargeReg), HasCall) ||
    292          !any_of(LIS.getInterval(SmallReg), HasCall);
    293 }
    294 
    295 
    296 unsigned HexagonRegisterInfo::getRARegister() const {
    297   return Hexagon::R31;
    298 }
    299 
    300 
    301 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
    302                                                &MF) const {
    303   const HexagonFrameLowering *TFI = getFrameLowering(MF);
    304   if (TFI->hasFP(MF))
    305     return getFrameRegister();
    306   return getStackRegister();
    307 }
    308 
    309 
    310 unsigned HexagonRegisterInfo::getFrameRegister() const {
    311   return Hexagon::R30;
    312 }
    313 
    314 
    315 unsigned HexagonRegisterInfo::getStackRegister() const {
    316   return Hexagon::R29;
    317 }
    318 
    319 
    320 unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
    321       const TargetRegisterClass &RC, unsigned GenIdx) const {
    322   assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
    323 
    324   static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
    325   static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
    326 
    327   switch (RC.getID()) {
    328     case Hexagon::CtrRegs64RegClassID:
    329     case Hexagon::DoubleRegsRegClassID:
    330       return ISub[GenIdx];
    331     case Hexagon::HvxWRRegClassID:
    332       return VSub[GenIdx];
    333   }
    334 
    335   if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
    336     return getHexagonSubRegIndex(*SuperRC, GenIdx);
    337 
    338   llvm_unreachable("Invalid register class");
    339 }
    340 
    341 bool HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF)
    342       const {
    343   return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
    344 }
    345 
    346 const TargetRegisterClass *
    347 HexagonRegisterInfo::getPointerRegClass(const MachineFunction &MF,
    348                                         unsigned Kind) const {
    349   return &Hexagon::IntRegsRegClass;
    350 }
    351 
    352 unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const {
    353   return Hexagon::R6;
    354 }
    355 
    356