| /external/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 126 bool IsKill = false;
142 IsKill = true;
144 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
|
| MipsSERegisterInfo.cpp | 157 bool IsKill = false;
192 IsKill = true;
209 IsKill = true;
213 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 126 bool IsKill = false;
142 IsKill = true;
144 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
|
| MipsSERegisterInfo.cpp | 201 bool IsKill = false;
238 IsKill = true;
255 IsKill = true;
259 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
|
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 47 unsigned SrcReg, bool IsKill, int FI,
56 .addReg(SrcReg, getKillRegState(IsKill))
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| RISCVInstrInfo.h | 41 bool IsKill, int FrameIndex,
|
| RISCVInstrInfo.cpp | 111 unsigned SrcReg, bool IsKill, int FI,
131 .addReg(SrcReg, getKillRegState(IsKill))
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 179 bool IsKill = false;
205 IsKill = true;
208 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
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| HexagonFrameLowering.cpp | [all...] |
| HexagonFrameLowering.h | 142 bool IsDef, bool IsKill) const;
|
| HexagonBlockRanges.cpp | 318 bool IsKill = Op.isKill();
321 if (IsKill)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 127 unsigned SrcReg, bool IsKill, int FI,
136 .addReg(SrcReg, getKillRegState(IsKill))
141 .addReg(SrcReg, getKillRegState(IsKill))
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 82 /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
93 /// IsKill - True if this instruction is the last use of the register on this
95 bool IsKill : 1;
297 bool isKill() const {
299 return IsKill;
378 IsKill = Val;
551 /// operand. Note: This method ignores isKill and isDead properties.
581 bool isKill = false, bool isDead = false,
607 bool isKill = false, bool isDead = false,
614 assert(!(isKill && isDef) && "Kill flag on def")
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.h | 57 unsigned SourceRegister, bool IsKill, int FrameIndex,
|
| LanaiInstrInfo.cpp | 52 unsigned SourceRegister, bool IsKill, int FrameIndex,
64 .addReg(SourceRegister, getKillRegState(IsKill))
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| MachineOperand.h | 67 /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register
78 /// IsKill - True if this instruction is the last use of the register on this
80 bool IsKill : 1;
251 bool isKill() const {
253 return IsKill;
333 IsKill = Val;
452 /// operand. Note: This method ignores isKill and isDead properties.
464 bool isKill = false, bool isDead = false,
490 bool isKill = false, bool isDead = false,
498 Op.IsKill = isKill
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.h | 58 unsigned SourceRegister, bool IsKill, int FrameIndex,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 213 bool IsKill = false;
239 IsKill = true;
242 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
|
| HexagonFrameLowering.cpp | [all...] |
| HexagonFrameLowering.h | 168 bool IsDef, bool IsKill) const;
|
| HexagonBlockRanges.cpp | 327 bool IsKill = Op.isKill();
330 if (IsKill)
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 283 unsigned Dst, unsigned Src, bool IsKill) {
286 .addReg(Src, getKillRegState(IsKill));
318 KillSrc0 = MOSrc0->isKill();
337 KillSrc1 = MOSrc1->isKill();
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 276 unsigned Dst, unsigned Src, bool IsKill) {
279 .addReg(Src, getKillRegState(IsKill));
311 KillSrc0 = MOSrc0->isKill();
330 KillSrc1 = MOSrc1->isKill();
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 419 bool IsKill = SrcDst->isKill();
473 SrcDstRegState |= getKillRegState(IsKill);
521 bool IsKill = MI->getOperand(0).isKill();
523 unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill);
535 .addReg(SubReg, getKillRegState(IsKill))
555 SuperKillState |= getKillRegState(IsKill);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 519 bool IsKill,
593 SrcDstRegState |= getKillRegState(IsKill);
602 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill))
659 bool IsKill = MI->getOperand(0).isKill();
699 unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill);
735 .addReg(SubReg, getKillRegState(IsKill)) // sdata
759 .addReg(SubReg, getKillRegState(IsKill))
787 SuperKillState |= getKillRegState(IsKill);
[all...] |
