| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 66 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
|
| HexagonRegisterInfo.cpp | 247 bool HexagonRegisterInfo::shouldCoalesce(MachineInstr *MI,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.h | 81 bool shouldCoalesce(MachineInstr *MI,
|
| SystemZRegisterInfo.cpp | 247 bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 190 bool shouldCoalesce(MachineInstr *MI,
|
| ARMBaseRegisterInfo.cpp | 783 bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
820 DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
822 DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 205 bool shouldCoalesce(MachineInstr *MI,
|
| ARMBaseRegisterInfo.cpp | 802 bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
841 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
843 LLVM_DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.h | 209 bool shouldCoalesce(MachineInstr *MI,
|
| SIRegisterInfo.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| TargetRegisterInfo.h | [all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | [all...] |
