1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * MCF5275 Internal Memory Map 4 * 5 * Copyright (C) 2003-2004, Greg Ungerer (gerg (at) snapgear.com) 6 * Copyright (C) 2004-2008 Arthur Shipkowski (art (at) videon-central.com) 7 */ 8 9 #ifndef __M5275_H__ 10 #define __M5275_H__ 11 12 /* 13 * Define the 5275 SIM register set addresses. These are similar, 14 * but not quite identical to the 5282 registers and offsets. 15 */ 16 #define MCF_GPIO_PAR_UART 0x10007c 17 #define UART0_ENABLE_MASK 0x000f 18 #define UART1_ENABLE_MASK 0x00f0 19 #define UART2_ENABLE_MASK 0x3f00 20 21 #define MCF_GPIO_PAR_FECI2C 0x100082 22 #define PAR_SDA_ENABLE_MASK 0x0003 23 #define PAR_SCL_ENABLE_MASK 0x000c 24 25 #define MCFSIM_WRRR 0x140000 26 #define MCFSIM_SDCR 0x40 27 28 /********************************************************************* 29 * SDRAM Controller (SDRAMC) 30 *********************************************************************/ 31 32 /* Register read/write macros */ 33 #define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040])) 34 #define MCF_SDRAMC_SDCR (*(vuint32*)(void*)(&__IPSBAR[0x000044])) 35 #define MCF_SDRAMC_SDCFG1 (*(vuint32*)(void*)(&__IPSBAR[0x000048])) 36 #define MCF_SDRAMC_SDCFG2 (*(vuint32*)(void*)(&__IPSBAR[0x00004C])) 37 #define MCF_SDRAMC_SDBAR0 (*(vuint32*)(void*)(&__IPSBAR[0x000050])) 38 #define MCF_SDRAMC_SDBAR1 (*(vuint32*)(void*)(&__IPSBAR[0x000058])) 39 #define MCF_SDRAMC_SDMR0 (*(vuint32*)(void*)(&__IPSBAR[0x000054])) 40 #define MCF_SDRAMC_SDMR1 (*(vuint32*)(void*)(&__IPSBAR[0x00005C])) 41 42 /* Bit definitions and macros for MCF_SDRAMC_SDMR */ 43 #define MCF_SDRAMC_SDMR_CMD (0x00010000) 44 #define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) 45 #define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) 46 #define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) 47 #define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) 48 49 /* Bit definitions and macros for MCF_SDRAMC_SDCR */ 50 #define MCF_SDRAMC_SDCR_IPALL (0x00000002) 51 #define MCF_SDRAMC_SDCR_IREF (0x00000004) 52 #define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) 53 #define MCF_SDRAMC_SDCR_DQP_BP (0x00008000) 54 #define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) 55 #define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) 56 #define MCF_SDRAMC_SDCR_REF (0x10000000) 57 #define MCF_SDRAMC_SDCR_CKE (0x40000000) 58 #define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) 59 60 /* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ 61 #define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) 62 #define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) 63 #define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) 64 #define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) 65 #define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) 66 #define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) 67 #define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) 68 69 /* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ 70 #define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) 71 #define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) 72 #define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) 73 #define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) 74 75 /* Bit definitions and macros for MCF_SDRAMC_SDBARn */ 76 #define MCF_SDRAMC_SDBARn_BASE(x) (((x)&0x00003FFF)<<18) 77 #define MCF_SDRAMC_SDBARn_BA(x) ((x)&0xFFFF0000) 78 79 /* Bit definitions and macros for MCF_SDRAMC_SDMRn */ 80 #define MCF_SDRAMC_SDMRn_V (0x00000001) 81 #define MCF_SDRAMC_SDMRn_WP (0x00000080) 82 #define MCF_SDRAMC_SDMRn_MASK(x) (((x)&0x00003FFF)<<18) 83 #define MCF_SDRAMC_SDMRn_BAM_4G (0xFFFF0000) 84 #define MCF_SDRAMC_SDMRn_BAM_2G (0x7FFF0000) 85 #define MCF_SDRAMC_SDMRn_BAM_1G (0x3FFF0000) 86 #define MCF_SDRAMC_SDMRn_BAM_1024M (0x3FFF0000) 87 #define MCF_SDRAMC_SDMRn_BAM_512M (0x1FFF0000) 88 #define MCF_SDRAMC_SDMRn_BAM_256M (0x0FFF0000) 89 #define MCF_SDRAMC_SDMRn_BAM_128M (0x07FF0000) 90 #define MCF_SDRAMC_SDMRn_BAM_64M (0x03FF0000) 91 #define MCF_SDRAMC_SDMRn_BAM_32M (0x01FF0000) 92 #define MCF_SDRAMC_SDMRn_BAM_16M (0x00FF0000) 93 #define MCF_SDRAMC_SDMRn_BAM_8M (0x007F0000) 94 #define MCF_SDRAMC_SDMRn_BAM_4M (0x003F0000) 95 #define MCF_SDRAMC_SDMRn_BAM_2M (0x001F0000) 96 #define MCF_SDRAMC_SDMRn_BAM_1M (0x000F0000) 97 #define MCF_SDRAMC_SDMRn_BAM_1024K (0x000F0000) 98 #define MCF_SDRAMC_SDMRn_BAM_512K (0x00070000) 99 #define MCF_SDRAMC_SDMRn_BAM_256K (0x00030000) 100 #define MCF_SDRAMC_SDMRn_BAM_128K (0x00010000) 101 #define MCF_SDRAMC_SDMRn_BAM_64K (0x00000000) 102 103 /********************************************************************* 104 * Interrupt Controller (INTC) 105 ********************************************************************/ 106 #define INT0_LO_RSVD0 (0) 107 #define INT0_LO_EPORT1 (1) 108 #define INT0_LO_EPORT2 (2) 109 #define INT0_LO_EPORT3 (3) 110 #define INT0_LO_EPORT4 (4) 111 #define INT0_LO_EPORT5 (5) 112 #define INT0_LO_EPORT6 (6) 113 #define INT0_LO_EPORT7 (7) 114 #define INT0_LO_SCM (8) 115 #define INT0_LO_DMA0 (9) 116 #define INT0_LO_DMA1 (10) 117 #define INT0_LO_DMA2 (11) 118 #define INT0_LO_DMA3 (12) 119 #define INT0_LO_UART0 (13) 120 #define INT0_LO_UART1 (14) 121 #define INT0_LO_UART2 (15) 122 #define INT0_LO_RSVD1 (16) 123 #define INT0_LO_I2C (17) 124 #define INT0_LO_QSPI (18) 125 #define INT0_LO_DTMR0 (19) 126 #define INT0_LO_DTMR1 (20) 127 #define INT0_LO_DTMR2 (21) 128 #define INT0_LO_DTMR3 (22) 129 #define INT0_LO_FEC0_TXF (23) 130 #define INT0_LO_FEC0_TXB (24) 131 #define INT0_LO_FEC0_UN (25) 132 #define INT0_LO_FEC0_RL (26) 133 #define INT0_LO_FEC0_RXF (27) 134 #define INT0_LO_FEC0_RXB (28) 135 #define INT0_LO_FEC0_MII (29) 136 #define INT0_LO_FEC0_LC (30) 137 #define INT0_LO_FEC0_HBERR (31) 138 #define INT0_HI_FEC0_GRA (32) 139 #define INT0_HI_FEC0_EBERR (33) 140 #define INT0_HI_FEC0_BABT (34) 141 #define INT0_HI_FEC0_BABR (35) 142 #define INT0_HI_PIT0 (36) 143 #define INT0_HI_PIT1 (37) 144 #define INT0_HI_PIT2 (38) 145 #define INT0_HI_PIT3 (39) 146 #define INT0_HI_RNG (40) 147 #define INT0_HI_SKHA (41) 148 #define INT0_HI_MDHA (42) 149 #define INT0_HI_USB (43) 150 #define INT0_HI_USB_EP0 (44) 151 #define INT0_HI_USB_EP1 (45) 152 #define INT0_HI_USB_EP2 (46) 153 #define INT0_HI_USB_EP3 (47) 154 /* 48-63 Reserved */ 155 156 /* 0-22 Reserved */ 157 #define INT1_LO_FEC1_TXF (23) 158 #define INT1_LO_FEC1_TXB (24) 159 #define INT1_LO_FEC1_UN (25) 160 #define INT1_LO_FEC1_RL (26) 161 #define INT1_LO_FEC1_RXF (27) 162 #define INT1_LO_FEC1_RXB (28) 163 #define INT1_LO_FEC1_MII (29) 164 #define INT1_LO_FEC1_LC (30) 165 #define INT1_LO_FEC1_HBERR (31) 166 #define INT1_HI_FEC1_GRA (32) 167 #define INT1_HI_FEC1_EBERR (33) 168 #define INT1_HI_FEC1_BABT (34) 169 #define INT1_HI_FEC1_BABR (35) 170 /* 36-63 Reserved */ 171 172 /* Bit definitions and macros for RCR */ 173 #define RCM_RCR_FRCRSTOUT (0x40) 174 #define RCM_RCR_SOFTRST (0x80) 175 176 #define FMPLL_SYNSR_LOCK (0x00000008) 177 178 #endif /* __M5275_H__ */ 179
