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Searched
refs:Imm64
(Results
1 - 8
of
8
) sorted by null
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h
321
Imm64
= 7 << ImmShift,
436
case X86II::
Imm64
: return 8;
452
case X86II::
Imm64
:
/external/llvm/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h
411
Imm64
= 8 << ImmShift,
584
case X86II::
Imm64
: return 8;
601
case X86II::
Imm64
:
619
case X86II::
Imm64
:
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h
464
Imm64
= 9 << ImmShift,
604
case X86II::
Imm64
: return 8;
622
case X86II::
Imm64
:
641
case X86II::
Imm64
:
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp
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/external/llvm/lib/Target/PowerPC/
PPCISelDAGToDAG.cpp
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...]
/external/swiftshader/third_party/subzero/src/
IceAssemblerX86BaseImpl.h
319
AssemblerX86Base<TraitsType>::movabs(const GPRRegister Dst, uint64_t
Imm64
) {
321
const bool NeedsRexW = (
Imm64
& ~0xFFFFFFFFull) != 0;
325
// When emitting
Imm64
, we don't have to mask out the upper 32 bits for
328
emitInt32(
Imm64
& 0xFFFFFFFF);
330
emitInt32((
Imm64
>> 32) & 0xFFFFFFFF);
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all
...]
IceAssemblerX86Base.h
311
uint64_t
Imm64
);
[
all
...]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
AArch64GenGlobalISel.inc
424
int64_t
Imm64
= static_cast<int64_t>(Imm);
425
return
Imm64
>= std::numeric_limits<int32_t>::min() &&
426
Imm64
<= std::numeric_limits<int32_t>::max();
[
all
...]
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