| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 437 template <typename InsnType>
438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
441 template <typename InsnType>
442 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
445 template <typename InsnType>
446 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
449 template <typename InsnType>
450 static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
453 template <typename InsnType>
454 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address
[all...] |
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 437 template <typename InsnType>
438 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
441 template <typename InsnType>
443 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
446 template <typename InsnType>
448 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
451 template <typename InsnType>
453 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
456 template <typename InsnType>
458 DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address
[all...] |
| /external/capstone/arch/XCore/ |
| XCoreGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/Sparc/ |
| SparcGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/PowerPC/ |
| PPCGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, \
20 InsnType fieldMask; \
21 if (numBits == sizeof(InsnType)*8) \
22 fieldMask = (InsnType)(-1LL); \
24 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/SystemZ/ |
| SystemZGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/Mips/ |
| MipsGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCodeEmitter.cpp | 474 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI);
477 if (InsnType == HexagonII::TypeEXTENDER) {
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| MipsGenDisassemblerTables.inc | 19 template<typename InsnType>
23 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
25 assert(startBit + numBits <= (sizeof(InsnType)*8) &&
27 InsnType fieldMask;
28 if (numBits == sizeof(InsnType)*8)
29 fieldMask = (InsnType)(-1LL);
31 fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
[all...] |
| /external/capstone/arch/AArch64/ |
| AArch64GenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/capstone/arch/ARM/ |
| ARMGenDisassemblerTables.inc | 16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
19 InsnType fieldMask; \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| ARMGenDisassemblerTables.inc | 19 template<typename InsnType>
23 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
25 assert(startBit + numBits <= (sizeof(InsnType)*8) &&
27 InsnType fieldMask;
28 if (numBits == sizeof(InsnType)*8)
29 fieldMask = (InsnType)(-1LL);
31 fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| AArch64GenDisassemblerTables.inc | 19 template<typename InsnType>
23 static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
25 assert(startBit + numBits <= (sizeof(InsnType)*8) &&
27 InsnType fieldMask;
28 if (numBits == sizeof(InsnType)*8)
29 fieldMask = (InsnType)(-1LL);
31 fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
[all...] |
