1 //===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/HexagonMCCodeEmitter.h" 11 #include "Hexagon.h" 12 #include "MCTargetDesc/HexagonBaseInfo.h" 13 #include "MCTargetDesc/HexagonFixupKinds.h" 14 #include "MCTargetDesc/HexagonMCExpr.h" 15 #include "MCTargetDesc/HexagonMCInstrInfo.h" 16 #include "MCTargetDesc/HexagonMCTargetDesc.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCFixup.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCInstrDesc.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/Casting.h" 27 #include "llvm/Support/Compiler.h" 28 #include "llvm/Support/Debug.h" 29 #include "llvm/Support/Endian.h" 30 #include "llvm/Support/EndianStream.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/raw_ostream.h" 33 #include <cassert> 34 #include <cstddef> 35 #include <cstdint> 36 #include <map> 37 #include <string> 38 #include <vector> 39 40 #define DEBUG_TYPE "mccodeemitter" 41 42 using namespace llvm; 43 using namespace Hexagon; 44 45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 46 47 static const unsigned fixup_Invalid = ~0u; 48 49 #define _ fixup_Invalid 50 #define P(x) Hexagon::fixup_Hexagon##x 51 static const std::map<unsigned, std::vector<unsigned>> ExtFixups = { 52 { MCSymbolRefExpr::VK_DTPREL, 53 { _, _, _, _, 54 _, _, P(_DTPREL_16_X), P(_DTPREL_11_X), 55 P(_DTPREL_11_X), P(_9_X), _, P(_DTPREL_11_X), 56 P(_DTPREL_16_X), _, _, _, 57 P(_DTPREL_16_X), _, _, _, 58 _, _, _, _, 59 _, _, _, _, 60 _, _, _, _, 61 P(_DTPREL_32_6_X) }}, 62 { MCSymbolRefExpr::VK_GOT, 63 { _, _, _, _, 64 _, _, P(_GOT_11_X), _ /* [1] */, 65 _ /* [1] */, P(_9_X), _, P(_GOT_11_X), 66 P(_GOT_16_X), _, _, _, 67 P(_GOT_16_X), _, _, _, 68 _, _, _, _, 69 _, _, _, _, 70 _, _, _, _, 71 P(_GOT_32_6_X) }}, 72 { MCSymbolRefExpr::VK_GOTREL, 73 { _, _, _, _, 74 _, _, P(_GOTREL_11_X), P(_GOTREL_11_X), 75 P(_GOTREL_11_X), P(_9_X), _, P(_GOTREL_11_X), 76 P(_GOTREL_16_X), _, _, _, 77 P(_GOTREL_16_X), _, _, _, 78 _, _, _, _, 79 _, _, _, _, 80 _, _, _, _, 81 P(_GOTREL_32_6_X) }}, 82 { MCSymbolRefExpr::VK_TPREL, 83 { _, _, _, _, 84 _, _, P(_TPREL_16_X), P(_TPREL_11_X), 85 P(_TPREL_11_X), P(_9_X), _, P(_TPREL_11_X), 86 P(_TPREL_16_X), _, _, _, 87 P(_TPREL_16_X), _, _, _, 88 _, _, _, _, 89 _, _, _, _, 90 _, _, _, _, 91 P(_TPREL_32_6_X) }}, 92 { MCSymbolRefExpr::VK_Hexagon_GD_GOT, 93 { _, _, _, _, 94 _, _, P(_GD_GOT_16_X), P(_GD_GOT_11_X), 95 P(_GD_GOT_11_X), P(_9_X), _, P(_GD_GOT_11_X), 96 P(_GD_GOT_16_X), _, _, _, 97 P(_GD_GOT_16_X), _, _, _, 98 _, _, _, _, 99 _, _, _, _, 100 _, _, _, _, 101 P(_GD_GOT_32_6_X) }}, 102 { MCSymbolRefExpr::VK_Hexagon_GD_PLT, 103 { _, _, _, _, 104 _, _, _, _, 105 _, P(_9_X), _, P(_GD_PLT_B22_PCREL_X), 106 _, _, _, _, 107 _, _, _, _, 108 _, _, P(_GD_PLT_B22_PCREL_X), _, 109 _, _, _, _, 110 _, _, _, _, 111 _ }}, 112 { MCSymbolRefExpr::VK_Hexagon_IE, 113 { _, _, _, _, 114 _, _, P(_IE_16_X), _, 115 _, P(_9_X), _, _, 116 P(_IE_16_X), _, _, _, 117 P(_IE_16_X), _, _, _, 118 _, _, _, _, 119 _, _, _, _, 120 _, _, _, _, 121 P(_IE_32_6_X) }}, 122 { MCSymbolRefExpr::VK_Hexagon_IE_GOT, 123 { _, _, _, _, 124 _, _, P(_IE_GOT_11_X), P(_IE_GOT_11_X), 125 P(_IE_GOT_11_X), P(_9_X), _, P(_IE_GOT_11_X), 126 P(_IE_GOT_16_X), _, _, _, 127 P(_IE_GOT_16_X), _, _, _, 128 _, _, _, _, 129 _, _, _, _, 130 _, _, _, _, 131 P(_IE_GOT_32_6_X) }}, 132 { MCSymbolRefExpr::VK_Hexagon_LD_GOT, 133 { _, _, _, _, 134 _, _, P(_LD_GOT_11_X), P(_LD_GOT_11_X), 135 P(_LD_GOT_11_X), P(_9_X), _, P(_LD_GOT_11_X), 136 P(_LD_GOT_16_X), _, _, _, 137 P(_LD_GOT_16_X), _, _, _, 138 _, _, _, _, 139 _, _, _, _, 140 _, _, _, _, 141 P(_LD_GOT_32_6_X) }}, 142 { MCSymbolRefExpr::VK_Hexagon_LD_PLT, 143 { _, _, _, _, 144 _, _, _, _, 145 _, P(_9_X), _, P(_LD_PLT_B22_PCREL_X), 146 _, _, _, _, 147 _, _, _, _, 148 _, _, P(_LD_PLT_B22_PCREL_X), _, 149 _, _, _, _, 150 _, _, _, _, 151 _ }}, 152 { MCSymbolRefExpr::VK_Hexagon_PCREL, 153 { _, _, _, _, 154 _, _, P(_6_PCREL_X), _, 155 _, P(_9_X), _, _, 156 _, _, _, _, 157 _, _, _, _, 158 _, _, _, _, 159 _, _, _, _, 160 _, _, _, _, 161 P(_32_PCREL) }}, 162 { MCSymbolRefExpr::VK_None, 163 { _, _, _, _, 164 _, _, P(_6_X), P(_8_X), 165 P(_8_X), P(_9_X), P(_10_X), P(_11_X), 166 P(_12_X), P(_B13_PCREL), _, P(_B15_PCREL_X), 167 P(_16_X), _, _, _, 168 _, _, P(_B22_PCREL_X), _, 169 _, _, _, _, 170 _, _, _, _, 171 P(_32_6_X) }}, 172 }; 173 // [1] The fixup is GOT_16_X for signed values and GOT_11_X for unsigned. 174 175 static const std::map<unsigned, std::vector<unsigned>> StdFixups = { 176 { MCSymbolRefExpr::VK_DTPREL, 177 { _, _, _, _, 178 _, _, _, _, 179 _, _, _, _, 180 _, _, _, _, 181 P(_DTPREL_16), _, _, _, 182 _, _, _, _, 183 _, _, _, _, 184 _, _, _, _, 185 P(_DTPREL_32) }}, 186 { MCSymbolRefExpr::VK_GOT, 187 { _, _, _, _, 188 _, _, _, _, 189 _, _, _, _, 190 _, _, _, _, 191 _, _, _, _, 192 _, _, _, _, 193 _, _, _, _, 194 _, _, _, _, 195 P(_GOT_32) }}, 196 { MCSymbolRefExpr::VK_GOTREL, 197 { _, _, _, _, 198 _, _, _, _, 199 _, _, _, _, 200 _, _, _, _, 201 _ /* [2] */, _, _, _, 202 _, _, _, _, 203 _, _, _, _, 204 _, _, _, _, 205 P(_GOTREL_32) }}, 206 { MCSymbolRefExpr::VK_PLT, 207 { _, _, _, _, 208 _, _, _, _, 209 _, _, _, _, 210 _, _, _, _, 211 _, _, _, _, 212 _, _, P(_PLT_B22_PCREL), _, 213 _, _, _, _, 214 _, _, _, _, 215 _ }}, 216 { MCSymbolRefExpr::VK_TPREL, 217 { _, _, _, _, 218 _, _, _, _, 219 _, _, _, P(_TPREL_11_X), 220 _, _, _, _, 221 P(_TPREL_16), _, _, _, 222 _, _, _, _, 223 _, _, _, _, 224 _, _, _, _, 225 P(_TPREL_32) }}, 226 { MCSymbolRefExpr::VK_Hexagon_GD_GOT, 227 { _, _, _, _, 228 _, _, _, _, 229 _, _, _, _, 230 _, _, _, _, 231 P(_GD_GOT_16), _, _, _, 232 _, _, _, _, 233 _, _, _, _, 234 _, _, _, _, 235 P(_GD_GOT_32) }}, 236 { MCSymbolRefExpr::VK_Hexagon_GD_PLT, 237 { _, _, _, _, 238 _, _, _, _, 239 _, _, _, _, 240 _, _, _, _, 241 _, _, _, _, 242 _, _, P(_GD_PLT_B22_PCREL), _, 243 _, _, _, _, 244 _, _, _, _, 245 _ }}, 246 { MCSymbolRefExpr::VK_Hexagon_GPREL, 247 { _, _, _, _, 248 _, _, _, _, 249 _, _, _, _, 250 _, _, _, _, 251 P(_GPREL16_0), _, _, _, 252 _, _, _, _, 253 _, _, _, _, 254 _, _, _, _, 255 _ }}, 256 { MCSymbolRefExpr::VK_Hexagon_HI16, 257 { _, _, _, _, 258 _, _, _, _, 259 _, _, _, _, 260 _, _, _, _, 261 P(_HI16), _, _, _, 262 _, _, _, _, 263 _, _, _, _, 264 _, _, _, _, 265 _ }}, 266 { MCSymbolRefExpr::VK_Hexagon_IE, 267 { _, _, _, _, 268 _, _, _, _, 269 _, _, _, _, 270 _, _, _, _, 271 _, _, _, _, 272 _, _, _, _, 273 _, _, _, _, 274 _, _, _, _, 275 P(_IE_32) }}, 276 { MCSymbolRefExpr::VK_Hexagon_IE_GOT, 277 { _, _, _, _, 278 _, _, _, _, 279 _, _, _, _, 280 _, _, _, _, 281 P(_IE_GOT_16), _, _, _, 282 _, _, _, _, 283 _, _, _, _, 284 _, _, _, _, 285 P(_IE_GOT_32) }}, 286 { MCSymbolRefExpr::VK_Hexagon_LD_GOT, 287 { _, _, _, _, 288 _, _, _, _, 289 _, _, _, _, 290 _, _, _, _, 291 P(_LD_GOT_16), _, _, _, 292 _, _, _, _, 293 _, _, _, _, 294 _, _, _, _, 295 P(_LD_GOT_32) }}, 296 { MCSymbolRefExpr::VK_Hexagon_LD_PLT, 297 { _, _, _, _, 298 _, _, _, _, 299 _, _, _, _, 300 _, _, _, _, 301 _, _, _, _, 302 _, _, P(_LD_PLT_B22_PCREL), _, 303 _, _, _, _, 304 _, _, _, _, 305 _ }}, 306 { MCSymbolRefExpr::VK_Hexagon_LO16, 307 { _, _, _, _, 308 _, _, _, _, 309 _, _, _, _, 310 _, _, _, _, 311 P(_LO16), _, _, _, 312 _, _, _, _, 313 _, _, _, _, 314 _, _, _, _, 315 _ }}, 316 { MCSymbolRefExpr::VK_Hexagon_PCREL, 317 { _, _, _, _, 318 _, _, _, _, 319 _, _, _, _, 320 _, _, _, _, 321 _, _, _, _, 322 _, _, _, _, 323 _, _, _, _, 324 _, _, _, _, 325 P(_32_PCREL) }}, 326 { MCSymbolRefExpr::VK_None, 327 { _, _, _, _, 328 _, _, _, _, 329 _, _, _, _, 330 _, P(_B13_PCREL), _, P(_B15_PCREL), 331 _, _, _, _, 332 _, _, P(_B22_PCREL), _, 333 _, _, _, _, 334 _, _, _, _, 335 P(_32) }}, 336 }; 337 // 338 // [2] The actual fixup is LO16 or HI16, depending on the instruction. 339 #undef P 340 #undef _ 341 342 uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB, 343 MCInst const &MCI) const { 344 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); 345 if (State.Index == 0) { 346 if (HexagonMCInstrInfo::isInnerLoop(MCB)) { 347 assert(!Duplex); 348 assert(State.Index != Last); 349 return HexagonII::INST_PARSE_LOOP_END; 350 } 351 } 352 if (State.Index == 1) { 353 if (HexagonMCInstrInfo::isOuterLoop(MCB)) { 354 assert(!Duplex); 355 assert(State.Index != Last); 356 return HexagonII::INST_PARSE_LOOP_END; 357 } 358 } 359 if (Duplex) { 360 assert(State.Index == Last); 361 return HexagonII::INST_PARSE_DUPLEX; 362 } 363 if (State.Index == Last) 364 return HexagonII::INST_PARSE_PACKET_END; 365 return HexagonII::INST_PARSE_NOT_END; 366 } 367 368 /// Emit the bundle. 369 void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 370 SmallVectorImpl<MCFixup> &Fixups, 371 const MCSubtargetInfo &STI) const { 372 MCInst &HMB = const_cast<MCInst &>(MI); 373 374 assert(HexagonMCInstrInfo::isBundle(HMB)); 375 LLVM_DEBUG(dbgs() << "Encoding bundle\n";); 376 State.Addend = 0; 377 State.Extended = false; 378 State.Bundle = &MI; 379 State.Index = 0; 380 size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1; 381 uint64_t Features = computeAvailableFeatures(STI.getFeatureBits()); 382 383 for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) { 384 MCInst &HMI = const_cast<MCInst &>(*I.getInst()); 385 verifyInstructionPredicates(HMI, Features); 386 387 EncodeSingleInstruction(HMI, OS, Fixups, STI, parseBits(Last, HMB, HMI)); 388 State.Extended = HexagonMCInstrInfo::isImmext(HMI); 389 State.Addend += HEXAGON_INSTR_SIZE; 390 ++State.Index; 391 } 392 } 393 394 static bool RegisterMatches(unsigned Consumer, unsigned Producer, 395 unsigned Producer2) { 396 if (Consumer == Producer) 397 return true; 398 if (Consumer == Producer2) 399 return true; 400 // Calculate if we're a single vector consumer referencing a double producer 401 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 402 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31) 403 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0); 404 return false; 405 } 406 407 /// EncodeSingleInstruction - Emit a single 408 void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI, 409 raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, 410 const MCSubtargetInfo &STI, uint32_t Parse) const { 411 assert(!HexagonMCInstrInfo::isBundle(MI)); 412 uint64_t Binary; 413 414 // Pseudo instructions don't get encoded and shouldn't be here 415 // in the first place! 416 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && 417 "pseudo-instruction found"); 418 LLVM_DEBUG(dbgs() << "Encoding insn `" 419 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); 420 421 Binary = getBinaryCodeForInstr(MI, Fixups, STI); 422 unsigned Opc = MI.getOpcode(); 423 424 // Check for unimplemented instructions. Immediate extenders 425 // are encoded as zero, so they need to be accounted for. 426 if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) { 427 LLVM_DEBUG(dbgs() << "Unimplemented inst `" 428 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); 429 llvm_unreachable("Unimplemented Instruction"); 430 } 431 Binary |= Parse; 432 433 // if we need to emit a duplexed instruction 434 if (Opc >= Hexagon::DuplexIClass0 && Opc <= Hexagon::DuplexIClassF) { 435 assert(Parse == HexagonII::INST_PARSE_DUPLEX && 436 "Emitting duplex without duplex parse bits"); 437 unsigned DupIClass = MI.getOpcode() - Hexagon::DuplexIClass0; 438 // 29 is the bit position. 439 // 0b1110 =0xE bits are masked off and down shifted by 1 bit. 440 // Last bit is moved to bit position 13 441 Binary = ((DupIClass & 0xE) << (29 - 1)) | ((DupIClass & 0x1) << 13); 442 443 const MCInst *Sub0 = MI.getOperand(0).getInst(); 444 const MCInst *Sub1 = MI.getOperand(1).getInst(); 445 446 // Get subinstruction slot 0. 447 unsigned SubBits0 = getBinaryCodeForInstr(*Sub0, Fixups, STI); 448 // Get subinstruction slot 1. 449 State.SubInst1 = true; 450 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI); 451 State.SubInst1 = false; 452 453 Binary |= SubBits0 | (SubBits1 << 16); 454 } 455 support::endian::write<uint32_t>(OS, Binary, support::little); 456 ++MCNumEmitted; 457 } 458 459 LLVM_ATTRIBUTE_NORETURN 460 static void raise_relocation_error(unsigned Width, unsigned Kind) { 461 std::string Text; 462 raw_string_ostream Stream(Text); 463 Stream << "Unrecognized relocation combination: width=" << Width 464 << " kind=" << Kind; 465 report_fatal_error(Stream.str()); 466 } 467 468 /// Some insns are not extended and thus have no bits. These cases require 469 /// a more brute force method for determining the correct relocation. 470 Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits( 471 MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, 472 const MCSymbolRefExpr::VariantKind VarKind) const { 473 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); 474 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI); 475 using namespace Hexagon; 476 477 if (InsnType == HexagonII::TypeEXTENDER) { 478 if (VarKind == MCSymbolRefExpr::VK_None) { 479 auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle); 480 for (auto I = Instrs.begin(), N = Instrs.end(); I != N; ++I) { 481 if (I->getInst() != &MI) 482 continue; 483 assert(I+1 != N && "Extender cannot be last in packet"); 484 const MCInst &NextI = *(I+1)->getInst(); 485 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI); 486 if (NextD.isBranch() || NextD.isCall() || 487 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR) 488 return fixup_Hexagon_B32_PCREL_X; 489 return fixup_Hexagon_32_6_X; 490 } 491 } 492 493 static const std::map<unsigned,unsigned> Relocs = { 494 { MCSymbolRefExpr::VK_GOTREL, fixup_Hexagon_GOTREL_32_6_X }, 495 { MCSymbolRefExpr::VK_GOT, fixup_Hexagon_GOT_32_6_X }, 496 { MCSymbolRefExpr::VK_TPREL, fixup_Hexagon_TPREL_32_6_X }, 497 { MCSymbolRefExpr::VK_DTPREL, fixup_Hexagon_DTPREL_32_6_X }, 498 { MCSymbolRefExpr::VK_Hexagon_GD_GOT, fixup_Hexagon_GD_GOT_32_6_X }, 499 { MCSymbolRefExpr::VK_Hexagon_LD_GOT, fixup_Hexagon_LD_GOT_32_6_X }, 500 { MCSymbolRefExpr::VK_Hexagon_IE, fixup_Hexagon_IE_32_6_X }, 501 { MCSymbolRefExpr::VK_Hexagon_IE_GOT, fixup_Hexagon_IE_GOT_32_6_X }, 502 { MCSymbolRefExpr::VK_Hexagon_PCREL, fixup_Hexagon_B32_PCREL_X }, 503 { MCSymbolRefExpr::VK_Hexagon_GD_PLT, fixup_Hexagon_GD_PLT_B32_PCREL_X }, 504 { MCSymbolRefExpr::VK_Hexagon_LD_PLT, fixup_Hexagon_LD_PLT_B32_PCREL_X }, 505 }; 506 507 auto F = Relocs.find(VarKind); 508 if (F != Relocs.end()) 509 return Hexagon::Fixups(F->second); 510 raise_relocation_error(0, VarKind); 511 } 512 513 if (MCID.isBranch()) 514 return fixup_Hexagon_B13_PCREL; 515 516 static const std::map<unsigned,unsigned> RelocsLo = { 517 { MCSymbolRefExpr::VK_GOT, fixup_Hexagon_GOT_LO16 }, 518 { MCSymbolRefExpr::VK_GOTREL, fixup_Hexagon_GOTREL_LO16 }, 519 { MCSymbolRefExpr::VK_Hexagon_GD_GOT, fixup_Hexagon_GD_GOT_LO16 }, 520 { MCSymbolRefExpr::VK_Hexagon_LD_GOT, fixup_Hexagon_LD_GOT_LO16 }, 521 { MCSymbolRefExpr::VK_Hexagon_IE, fixup_Hexagon_IE_LO16 }, 522 { MCSymbolRefExpr::VK_Hexagon_IE_GOT, fixup_Hexagon_IE_GOT_LO16 }, 523 { MCSymbolRefExpr::VK_TPREL, fixup_Hexagon_TPREL_LO16 }, 524 { MCSymbolRefExpr::VK_DTPREL, fixup_Hexagon_DTPREL_LO16 }, 525 { MCSymbolRefExpr::VK_None, fixup_Hexagon_LO16 }, 526 }; 527 528 static const std::map<unsigned,unsigned> RelocsHi = { 529 { MCSymbolRefExpr::VK_GOT, fixup_Hexagon_GOT_HI16 }, 530 { MCSymbolRefExpr::VK_GOTREL, fixup_Hexagon_GOTREL_HI16 }, 531 { MCSymbolRefExpr::VK_Hexagon_GD_GOT, fixup_Hexagon_GD_GOT_HI16 }, 532 { MCSymbolRefExpr::VK_Hexagon_LD_GOT, fixup_Hexagon_LD_GOT_HI16 }, 533 { MCSymbolRefExpr::VK_Hexagon_IE, fixup_Hexagon_IE_HI16 }, 534 { MCSymbolRefExpr::VK_Hexagon_IE_GOT, fixup_Hexagon_IE_GOT_HI16 }, 535 { MCSymbolRefExpr::VK_TPREL, fixup_Hexagon_TPREL_HI16 }, 536 { MCSymbolRefExpr::VK_DTPREL, fixup_Hexagon_DTPREL_HI16 }, 537 { MCSymbolRefExpr::VK_None, fixup_Hexagon_HI16 }, 538 }; 539 540 switch (MCID.getOpcode()) { 541 case Hexagon::LO: 542 case Hexagon::A2_tfril: { 543 auto F = RelocsLo.find(VarKind); 544 if (F != RelocsLo.end()) 545 return Hexagon::Fixups(F->second); 546 break; 547 } 548 case Hexagon::HI: 549 case Hexagon::A2_tfrih: { 550 auto F = RelocsHi.find(VarKind); 551 if (F != RelocsHi.end()) 552 return Hexagon::Fixups(F->second); 553 break; 554 } 555 } 556 557 raise_relocation_error(0, VarKind); 558 } 559 560 static bool isPCRel(unsigned Kind) { 561 switch (Kind){ 562 case fixup_Hexagon_B22_PCREL: 563 case fixup_Hexagon_B15_PCREL: 564 case fixup_Hexagon_B7_PCREL: 565 case fixup_Hexagon_B13_PCREL: 566 case fixup_Hexagon_B9_PCREL: 567 case fixup_Hexagon_B32_PCREL_X: 568 case fixup_Hexagon_B22_PCREL_X: 569 case fixup_Hexagon_B15_PCREL_X: 570 case fixup_Hexagon_B13_PCREL_X: 571 case fixup_Hexagon_B9_PCREL_X: 572 case fixup_Hexagon_B7_PCREL_X: 573 case fixup_Hexagon_32_PCREL: 574 case fixup_Hexagon_PLT_B22_PCREL: 575 case fixup_Hexagon_GD_PLT_B22_PCREL: 576 case fixup_Hexagon_LD_PLT_B22_PCREL: 577 case fixup_Hexagon_GD_PLT_B22_PCREL_X: 578 case fixup_Hexagon_LD_PLT_B22_PCREL_X: 579 case fixup_Hexagon_6_PCREL_X: 580 return true; 581 default: 582 return false; 583 } 584 } 585 586 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, 587 const MCOperand &MO, const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups, 588 const MCSubtargetInfo &STI) const { 589 if (isa<HexagonMCExpr>(ME)) 590 ME = &HexagonMCInstrInfo::getExpr(*ME); 591 int64_t Value; 592 if (ME->evaluateAsAbsolute(Value)) { 593 bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) || 594 HexagonMCInstrInfo::isExtended(MCII, MI); 595 // Only sub-instruction #1 can be extended in a duplex. If MI is a 596 // sub-instruction #0, it is not extended even if Extended is true 597 // (it can be true for the duplex as a whole). 598 bool IsSub0 = HexagonMCInstrInfo::isSubInstruction(MI) && !State.SubInst1; 599 if (State.Extended && InstExtendable && !IsSub0) { 600 unsigned OpIdx = ~0u; 601 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) { 602 if (&MO != &MI.getOperand(I)) 603 continue; 604 OpIdx = I; 605 break; 606 } 607 assert(OpIdx != ~0u); 608 if (OpIdx == HexagonMCInstrInfo::getExtendableOp(MCII, MI)) { 609 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 610 Value = (Value & 0x3f) << Shift; 611 } 612 } 613 return Value; 614 } 615 assert(ME->getKind() == MCExpr::SymbolRef || 616 ME->getKind() == MCExpr::Binary); 617 if (ME->getKind() == MCExpr::Binary) { 618 MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME); 619 getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI); 620 getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI); 621 return 0; 622 } 623 624 unsigned FixupKind = fixup_Invalid; 625 const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME); 626 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); 627 unsigned FixupWidth = HexagonMCInstrInfo::getExtentBits(MCII, MI) - 628 HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 629 MCSymbolRefExpr::VariantKind VarKind = MCSRE->getKind(); 630 unsigned Opc = MCID.getOpcode(); 631 unsigned IType = HexagonMCInstrInfo::getType(MCII, MI); 632 633 LLVM_DEBUG(dbgs() << "----------------------------------------\n" 634 << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI) 635 << "\nOpcode: " << Opc << "\nRelocation bits: " 636 << FixupWidth << "\nAddend: " << State.Addend 637 << "\nVariant: " << unsigned(VarKind) 638 << "\n----------------------------------------\n"); 639 640 // Pick the applicable fixup kind for the symbol. 641 // Handle special cases first, the rest will be looked up in the tables. 642 643 if (FixupWidth == 16 && !State.Extended) { 644 if (VarKind == MCSymbolRefExpr::VK_None) { 645 if (HexagonMCInstrInfo::s27_2_reloc(*MO.getExpr())) { 646 // A2_iconst. 647 FixupKind = Hexagon::fixup_Hexagon_27_REG; 648 } else { 649 // Look for GP-relative fixups. 650 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); 651 static const Hexagon::Fixups GPRelFixups[] = { 652 Hexagon::fixup_Hexagon_GPREL16_0, Hexagon::fixup_Hexagon_GPREL16_1, 653 Hexagon::fixup_Hexagon_GPREL16_2, Hexagon::fixup_Hexagon_GPREL16_3 654 }; 655 assert(Shift < array_lengthof(GPRelFixups)); 656 auto UsesGP = [] (const MCInstrDesc &D) { 657 for (const MCPhysReg *U = D.getImplicitUses(); U && *U; ++U) 658 if (*U == Hexagon::GP) 659 return true; 660 return false; 661 }; 662 if (UsesGP(MCID)) 663 FixupKind = GPRelFixups[Shift]; 664 } 665 } else if (VarKind == MCSymbolRefExpr::VK_GOTREL) { 666 // Select between LO/HI. 667 if (Opc == Hexagon::LO) 668 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16; 669 else if (Opc == Hexagon::HI) 670 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16; 671 } 672 } else { 673 bool BranchOrCR = MCID.isBranch() || IType == HexagonII::TypeCR; 674 switch (FixupWidth) { 675 case 9: 676 if (BranchOrCR) 677 FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X 678 : Hexagon::fixup_Hexagon_B9_PCREL; 679 break; 680 case 8: 681 case 7: 682 if (State.Extended && VarKind == MCSymbolRefExpr::VK_GOT) 683 FixupKind = HexagonMCInstrInfo::isExtentSigned(MCII, MI) 684 ? Hexagon::fixup_Hexagon_GOT_16_X 685 : Hexagon::fixup_Hexagon_GOT_11_X; 686 else if (FixupWidth == 7 && BranchOrCR) 687 FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X 688 : Hexagon::fixup_Hexagon_B7_PCREL; 689 break; 690 case 0: 691 FixupKind = getFixupNoBits(MCII, MI, MO, VarKind); 692 break; 693 } 694 } 695 696 if (FixupKind == fixup_Invalid) { 697 const auto &FixupTable = State.Extended ? ExtFixups : StdFixups; 698 699 auto FindVK = FixupTable.find(VarKind); 700 if (FindVK != FixupTable.end()) 701 FixupKind = FindVK->second[FixupWidth]; 702 } 703 704 if (FixupKind == fixup_Invalid) 705 raise_relocation_error(FixupWidth, VarKind); 706 707 const MCExpr *FixupExpr = MO.getExpr(); 708 if (State.Addend != 0 && isPCRel(FixupKind)) { 709 const MCExpr *C = MCConstantExpr::create(State.Addend, MCT); 710 FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT); 711 } 712 713 MCFixup Fixup = MCFixup::create(State.Addend, FixupExpr, 714 MCFixupKind(FixupKind), MI.getLoc()); 715 Fixups.push_back(Fixup); 716 // All of the information is in the fixup. 717 return 0; 718 } 719 720 unsigned 721 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, 722 SmallVectorImpl<MCFixup> &Fixups, 723 MCSubtargetInfo const &STI) const { 724 #ifndef NDEBUG 725 size_t OperandNumber = ~0U; 726 for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) 727 if (&MI.getOperand(i) == &MO) { 728 OperandNumber = i; 729 break; 730 } 731 assert((OperandNumber != ~0U) && "Operand not found"); 732 #endif 733 734 if (HexagonMCInstrInfo::isNewValue(MCII, MI) && 735 &MO == &HexagonMCInstrInfo::getNewValueOperand(MCII, MI)) { 736 // Calculate the new value distance to the associated producer 737 unsigned SOffset = 0; 738 unsigned VOffset = 0; 739 unsigned UseReg = MO.getReg(); 740 unsigned DefReg1, DefReg2; 741 742 auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle); 743 const MCOperand *I = Instrs.begin() + State.Index - 1; 744 745 for (;; --I) { 746 assert(I != Instrs.begin() - 1 && "Couldn't find producer"); 747 MCInst const &Inst = *I->getInst(); 748 if (HexagonMCInstrInfo::isImmext(Inst)) 749 continue; 750 751 DefReg1 = DefReg2 = 0; 752 ++SOffset; 753 if (HexagonMCInstrInfo::isVector(MCII, Inst)) { 754 // Vector instructions don't count scalars. 755 ++VOffset; 756 } 757 if (HexagonMCInstrInfo::hasNewValue(MCII, Inst)) 758 DefReg1 = HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg(); 759 if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst)) 760 DefReg2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg(); 761 if (!RegisterMatches(UseReg, DefReg1, DefReg2)) { 762 // This isn't the register we're looking for 763 continue; 764 } 765 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) { 766 // Producer is unpredicated 767 break; 768 } 769 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) && 770 "Unpredicated consumer depending on predicated producer"); 771 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) == 772 HexagonMCInstrInfo::isPredicatedTrue(MCII, MI)) 773 // Producer predicate sense matched ours. 774 break; 775 } 776 // Hexagon PRM 10.11 Construct Nt from distance 777 unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset 778 : SOffset; 779 Offset <<= 1; 780 Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2); 781 return Offset; 782 } 783 784 assert(!MO.isImm()); 785 if (MO.isReg()) { 786 unsigned Reg = MO.getReg(); 787 if (HexagonMCInstrInfo::isSubInstruction(MI) || 788 HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ) 789 return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg); 790 return MCT.getRegisterInfo()->getEncodingValue(Reg); 791 } 792 793 return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI); 794 } 795 796 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII, 797 MCRegisterInfo const &MRI, 798 MCContext &MCT) { 799 return new HexagonMCCodeEmitter(MII, MCT); 800 } 801 802 #define ENABLE_INSTR_PREDICATE_VERIFIER 803 #include "HexagonGenMCCodeEmitter.inc" 804
